Research On Algorithms And Hardware Implementation Of Intelligent Video Surveillance

Video surveillance is becoming more important as the first and most widely used method along with the development of economy and safety consciousness. It enables people to monitor some important areas remotely in real time. The method currently is on the trend of intelligent video surveillance, which has some advantages that humans have not and gradually released people from video surveillance. The intelligent video surveillance is based on video content analysis, which includes detecting objects, tracking and identifying them, and analyzing their behaviors. Accurate and reliable video content analysis algorithms are indispensable for the surveillance system. However these algorithms generally have to process huge data and consume more computing resources, which bring great challenge to real-time monitoring. Recently there appear some hardware modules or platforms based on FPGA or chip as the video analysis engine for intelligent video surveillance. The video analysis engine improves processing speed and makes the surveillance fluent. We pay more attention to both the algorithm of intelligent video surveillance and the hardware implementation of video analysis engine in the thesis. The main research work consists of four parts as follows.(1) We have studied the background model in motion detection, and proposed a background model algorithm using mixture of Gaussians and Laplacian pyramid decomposition. The Laplacian pyramid is employed to decompose the image into low-frequency and high-frequency parts. We only make use of the static and dynamic features of pixels in low-frequency parts to model the background using mixture of Gaussians. After the motion objects in low-frequency parts have been extracted, we begin to use high-frequency parts to restore the objects in original size. The method not only reduces the disturbance of high-frequency parts to the model, but also decreases the demand for the memory space. The method achieve good results based on the experiments we have done using test videos. We have also presented the method of improved temporal differencing and its hardware implementation, which significantly increase the detection speed and efficiency. (2) The features and improved forms of Adaboost algorithm have been analyzed in the thesis. We also made some research on its application in face detection and object tracking, and compared some tracking algorithms based on boosting.(3) Face detection cost huge computing resources and need the support of software and hardware. We have studied some hardware architectures of face detection based on Adaboost, and proposed a novel architecture parallelly computing Haar features. By dividing feature set into groups and defining corresponding processing element, we introduce a multi-group architecture to further improve its parallelly computing power. We adopt different prediction mechanisms for different stages in the classifiers in order to reduce the side effect of the increased pipeline depth. Hardware architecture for face detection based on ASIC has been presented in the end.(4) The chips used in video surveillance which include video content analysis are usually large in scale, which will generate a great number of test vectors. We have proposed two kinds of test vector compression methods, both of which are based on the compatibility among test vectors. Test vectors are grouped based on their compatibility relationship and the test vectors in the group are merged into one vector. One compression technology adopts FDR-BC to encode the merged vectors, and the other employs CBCT to encode three kinds of runs in the merged vectors. Experiments with the test sets show that the method can achieve higher compression ratio compared with some classic compression methods. We also designed two corresponding decoders.