Study Of The Total Dose Effect In SRAM-based FPGA Based On Circuit Simulation Techniques

Total Ionizing Dose effect would influence the whole chip uniformly. To study theTID effect in integrated circuits, experimental tests are usually carried out to inspect thedegradation of electrical macroscopic parameters, whereas an in-depth study isn’tpossible. Thus, it’s important to establish the connection between the TID mechanism ofdevices and the failure principle of VLSI circuits combining with the simulationmethod.Recently, space applications are developed quickly in our country. And the demandfor radiation-hardened SRAM-based FPGA is increasing continually. To shorten thetime of manufacturing and instruct the process of hardness-by-design, failure analysis ofchips and identification of comparative vulnerability of inner circuits are necessary to bedone. The contributions of this paper include:(1) The feasibility of applying circuit simulation for studying TID effect underdeep-submicron technology is evaluated.3-D device model for one0.25μm technologyis built using reverse-modeling method. The influence of doping density and electricfield along the STI sidewall on parasitic transistors turning on is analyzed. The resultsindicate that MOS devices would still work independently after irradiation.(2) The TID-aware circuit simulation method under deep-submicron technology isbuilt. Based on the development of TID-aware MOSFET model under the test-case biasduring irradiation, study of the equivalent relationship between the degradation ofparameters resulting from different bias during irradiation and realization withVerilog-A language, the connection between the TID mechanism of devices and theperformance degradation of circuits is established. During the simulation process, thereal bias states of every MOSFETs during irradiation are inspected and recordedcontinually. Then the performance degradation of circuits could be calculated.(3) Considering the uniformity of TID effect and diversity of working states ofcircuits, the concepts of sensitive node and the worst-case bias are introduced based oncharacteristics of CMOS circuits. Identification methods of the most sensitive node andthe corresponding bias condition are analyzed for different types of circuits. Then circuitsimulation could be executed dealing with specific sub-circuit and specific workingstate. This procedure can be used to simulate VLSI circuits. Besides, failure analysis of deep-submicron SRAM circuits is presented as an example.(4) Test scheme of TID effect in SRAM-based FPGA is established, which containsinspecting the supply current on-line, inspecting the output results of system andjudging the ability of re-configuration when arriving at the specific dose, in the end,testing the function of inner circuits after irradiation. Several kinds of inner circuitblocks are identified as circuits prone to be vulnerable after analyzing the failureprinciples preliminarily. Based on the circuit simulation methods built above, theseinner circuits are analyzed thoroughly and their hardness levels against TID arecalculated. Finally, the potential failure mechanisms are presented. After verificationbetween simulation and experiment results, the conclusion is proved to be correct.