Research On Low Power Processor Architecture For Electrocardiogram Signal Detection

Electrocardiogram signal detection based on wireless sensor nodes are getting more and more widely used. In order to improve the ease of use, the electrocardiogram signal processor must run under ultralow power consumption to extend the life time of the equipment.A low power processor is designed based on the commercial processor architecture in this paper. By introducing block instruction, the processor combines hardware and software optimization to reduce the power consumption under the processor architecture level. The main contents are as follows:Introduced migration algorithm to improve the existing learning mechanisms for enhancing the judge accuracy under imbalance data distribution.Introduced the method of block instruction to optimize power consumption. By the analysis of typical ECG applications, the characteristics of the ECG applications under instruction level were obtained:Operations of high repetition, memory access concentration, algorithm stability, less branch program. The processor uses block instruction rather than atomic instruction as basic unit to execute the program, hence, enlarges the optimization space and reduces the power consumption.Introduced the block instruction based complier, which transfer atomic instruction into block instruction。It includes dictionary assembly approach, register re-allocate, pre-decode, memory operation combination approach. The block instruction transfer module not only compress instruction space, but also reduce power consumption.Introduced the block instruction based processor which includes active memory, execution processor, variable length execution unit and low power memory access unit.Introduced active memory which automatically supplies pending block instruction and drives processor to execute it. Active memory enhances the flexibility of memory, reduces the bus transmission, decreases the difficulty for designing processor, and remove the instruction fetching and decoding logic.Introduced execution processor which leaps over redundant procedures and starts from the execution units. Introduced variable length execution unit which uses one module to support variable length single instruction multiple data operations.Introduced low power memory access unit based on hotspot initiative search and historical access trace. The unit will automatically judge hot process, dynamically buffer constant and the target hotspot location information to filter redundant data memory access.The proposed block instruction based method plays a positive role in reducing processor power. Experiments show that the low power processor based on block instruction can reduce the power consumption of 35%-40% compared with traditional processor.