Research And Implementation Of High Performance Low Dropout Linear Regulator

At present, microelectronics and semiconductor technologies have developed rapidly, power management chip has been used in telecommunication, computer, automotive electronic and many other fields. With the popularization of portable especially wearable electronic device, power management chip has found applications more widely. Hence the requirement made by users for the performance of power management chip is increasingly enhanced. Keeping in step with market and technology developments, aiming at low dropout regulator (LDO) that has the largest market share in power management products, this dissertation focuses on the optimization of the circuit design, improvement of chip load capacity, and reduction of static dissipation. Studies on stability of LDO and over current prevention theory are mainly made. And the involved technical problems are solved so that the integration and the reliability of the system are improved. The key innovations of this dissertation are as follows.1. There exist defects in frequency compensation circuit of traditional LDO. In order to overcome these defects, a novel compensation method with current buffer is presented in this part. The method suppresses the zero point in the right half-plane of this system based on the current buffer technique, which simplifies the system control loop and enhances the reliability of the system. Through sharing amplifier and current buffer circuits simultaneously, it avoids the additional power loss caused by the additional current buffer structure. The embedded frequency compensation method not only improves the current buffer stability, but also eliminates additional power consumption. According to the application requirements and product restrictions, this circuit employs a foreign process 0.6μm 5V 2P3M CMOS to achieve proven. This process shows good transient response under different application conditions and the quiescent current always is less than 50μA.2. A second order current limiting protection circuit is presented in this part to solve the defect of the traditional current limiting protection circuit in LDO. The circuit structure is simple and is integrated in LDO’s EA module. It improves voltage comparator structure by transforming sampled current into sampled voltage. Two branches are used in the current-limiting loop to realize real time control. This means its operational point changes with input voltage, and therefore the results that the value of current limiting is 80mA under the condition of first order protecting circuit,200mA of second order protecting circuit are obtained. The value of current limiting of the circuit is stable, not changing with the variations of the supply voltage substantially. This structure consumes low quiescent current only about 2μA at the same time. The protection circuit can be widely applied in different circuits. Test results show that the circuit can be started normally with different surface loads in both first order and second protective circuit.3. Traditional band-gap reference voltage varies with temperature variation, and the tendency chart looks like a parabola. Generally, the parabola vertex is set at 25℃ position, however this is not in accordance with the operation of LDO. As a member of power management chip, LDO is working at a higher temperature in actual working environment because it has integrated the power module in the system generally. Also the traditional band-gap reference’s temperature coefficient is not ideal on the position of parabola vertex. In order to avoid system’s output voltage decreasing with reference voltage at a high temperature reduction, a new bandgap-EA structure which contains high temperature compensated circuit is presented. Based on the Band-gap comparator structure the structure combines EA with band-gap reference skillfully. Through the introduction of high temperature compensated circuit, the shift of the reference voltage with temperature is limited and rapid declination of output voltage during operation at high temperatures is avoided. Thus, the voltage compensation effect is achieved, and the stability of LDO output voltage at high temperatures is improved.4. In order to meet the demands of loop stability and fast transient response in high voltage and low quiescent current applications, an adaptive impedance follower is presented in this part. The follower adjusts its output resistance by varying the output load current to make power transistor gate capacitor charge and discharge rapidly, which improves the transient response performance of the system. The follower and the parasitic capacitance of gate-source parasitic capacitor form a pole which moves to higher frequency to ensure that the station of pole will not affect the loop stability within the scope of full load current. The adaptive impedance follower ensures stability of this system while increasing the speed of the transient response of the circuit.5. Because the ultimate goal of the circuit design is to realize mass production tape-out, there are many necessary procedure and technical problems for a chip from the important circuit design to a practical power management chip. This dissertation designs a typical LDO chip XD1503 which has high output currents, high power supply rejection ratio and fast transient response. Analog IC design flow is introduced firstly in this part, the performance metrics of the chip is explained in detail, then the basic layout design rules and technologies are discussed, an analysis of test results including test data and test waveforms is made and conclusions are drawn finally.