| ATLAS liquid argon (LAr) calorimeter is an important part of the ATLAS detector, used to measure the particle energy produced by LHC (Large Hadron Collider). ATLAS LAr calorimeter plans to conduct Phase-I upgrade during the 2nd Long Shutdown (LS2) of LHC in 2018. In order to make ATLAS LAr calorimeter work under three times the current environment luminances during LHC Run-3 (2018-2019), the upgrade focus on the digital trigger system, thereby suppressing background noise, so as to select valid events from the background efficiently. Higher energy detection, luminosity and higher readout electronics granularity has caused significant amplification of the data transmission than ever. So optical link plays a crucial role in the high speed and mass data transmission of ATLAS LAr calorimeter trigger readout system. The main research work of this paper proposed the key coding scheme of data transmitter ASIC LOCx2 in optical data link, and implemented the core encoder module of LOCx2 under SoS 0.25 μm CMOS technology, designed the low latency optical data link back-end receiver FPGA firmware, and implemented the effective monitoring of the whole optical link system based on GBT-Link.The research contents and innovations of this paper are mainly manifested in the following aspects:1. ATLAS LAr calorimeter requires the front-end of the optical data link has radiation-resistant capability, the power consumption≤100 mW/Gbps, the latency≤75 ns, and the latency of the whole data link must be≤150 ns. The GBT-Link developed by CERN is the only optical link that can work in radiation environment in the world, but the other indicators do not meet the requirements. Therefore, SMU Optoelectronics Laboratory developed optical data link for ATLAS cooperation group to meet the requirements. The front-end of optical data link include a data transmitter ASIC LOCx2 and a laser driver ASIC LOCld2. Both ASICs are designed base on SoS 0.25μm CMOS technology, which uses sapphire as the insulating substrate, immunity to single event latch, has a natural radiation-resistant characteristics. The encoder in LOCx2 is the key module of low latency, low overhead and low power optical data link. The main research work is reflected in the following three points: ①We proposed a novel "LOCic code", the 12-bit BCID (Bunch Cross Identification) information is encoded in the 4-bit field creatively, the encoding overhead is reduced from 33.9% to 14.3% compared to the 8B10B coding for the transmission of 112-bit payload data per frame, greatly reducing the power consumption of the link. The simple encoding process make it easy to implement a low latency encoder circuit.②The layout of the encoder is manually designed carefully, the operating frequency is increased from the technology limit of 100MHz to 320MHz by optimizing the threshold voltage of digital cells, optimizing the clock tree, using pipeline and other methods, further reducing the latency. ③The interface with two ADC ASISs of the encoder is implemented by a special designed three clock FIFO, and can tolerate 3.125 ns phase uncertainty between two ADC output signals. LOCx2 has two transmitter channels, each outputs 5.12 Gbps serial data. Tests show that LOCx2 consumes only 843 mW, the latency of the entire chip is≤27.2 ns, latency produced by the encoder is≤21 ns, all indicators meet the ATLAS LAr calorimeter requirements.2. Besides the low latency encoder, a low latency data receiver is also required in order to reduce overall optical data link latency. The data receiver includes a deserializer and a decoder, is implemented by commercial FPGA: ①By optimizing serial transceiver IP core, make it capable of receiving 5.12 Gbps high speed serial data, recovering high speed clock, sampling data and deserializer data finally. ②With simple decoding process and making operate frequency of the decoder as high as possible,320MHz, the latency is reduced to the minimum. ③According to the characteristics of data when SEU(Single Event Upset) caused link loss, the decoder achieves a quick link re-synchronization. The optical data link test shows that the receiver can successfully synchronize the link, recover the raw data and BCID information, and pass the CRC check. The link bit error rate is<10-12, the latency of the whole data link is≤74.25 ns, far below 150 ns.3. In order to make the optical data link based on LOCx2 work properly, the corresponding control system is realized by using GBT-Link to provide clock, control signals and monitor system status for optical data link. In order to achieve bidirectional communication with the front-end GBTx and GBT-SCA ASICs, a GBT-Link protocol transceiver, a HDLC protocol transceiver and a channel command protocol transceiver is implemented on the back-end FPGA, finally through the GBTx and GBT-SCA ASIC to control and monitor LTDB. Tests show that under the control of the optical control link the optical data link can transmit data stable and reliable. |
PDF Full Text Request