Domain-specific Language Method And Modeling In SoC Design Optimization

Capabilities in digital VLSI front-end design technologies are not sufficient and flexible enough when IC industry enters into SoC era. By adopting domain-specific analysis, and facilitating compiler techonolgy, XML, fuzzy logic and multi-objective optimization, this paper carried out a series of researches on key technologies in SoC design optimization. Following research achievements were accomplished:.A domain specific language named MetaHDL was design and implemented for paramete-rizable configurable RTL design, ranging from logic oriented IP design to IP based SoC design. MetaHDL has a 2-level code configuration system consisting of automatic parameterization and comprehensive preprocessor, which helps designers create reusable design efficiently and achieves 20%-90% code reduction. MetaHDL syntax was specifically optimized for reusable RTL design to improve code readability and expressiveness. Built-in static code check mechanism guarantees the quality of ultimate generated SystemVerilog, reduces the expertise needed for RTL design, and improves the overall work quality and competitiveness of team.A fine-grained design reuse methodology named FGRX was proposed and an XML Schema based implementation was given. It provides reliable solution for heavy weighted SoC reuse scenario and platform-based SoC design scenario. FGRX extends the traditional methodology by enlarging the categories of reusable object. It encapsulates redundant codes by use translatione rules, and efficiently helps manage entire reuse project by automatically synchronizing contents of different files. FGRX's accumulative design style can achieve 10~2 to 10~3 times of code reduction, and this performance does not change when granularity or number of reusable objects changes.A transaction data flow based architecture level performance modeling methodology named TBPM was proposed. It uses directed acyclic graph to represent complex system. TBPM was implemented via a language named PML. Creating system performance model by PML can eliminate the complexity of logic description and flexibly manipulate all critical elements in model, which enables designers quickly validate several solutions in system dividing stage, and quanta-tively assess architecture design via data got from cycle accurate simulation. Designed and implemented a descrete particle swarm optimization algorithm for cooperation with TBPM to automatically optimize architecture level performance parameter setting and explore architecture design space. PML was extended to support optimization goal specification, parameter ranges definition, and design costs specification. Algorithm generates performance model and runs simulation on performance model automatically to get actually value of every performance goal, which is further synthesized via fuzzy logic according to designers' preference and desission weights to find out best fit solutions. As a glue layer of problem description, PML separated performance model, performance goal, and optimization algorithm, which modulizes each part and makes it possible to add more optimization algorithms. Introduced a complementary ossilcating parameter control mechanism that can drive all particles quickly approach to optimized solutions in this problem. Used OWA operator to synthesize high dimentional goal value vector into scalar value, which turns high dimentional vector Pareto sorting into simple scalar value sorting, and dramatically reduces computation complexity. Database and cluster based algorithm implementation provides a robust asynchronous communication mechanism among different components, fully facilitates available computation resources, and demonstrates good compliance in difference deployment environments.All research works were used in severl real chip development projects for validation, and proven to be very effective in efficiency and quality improvement in SoC design.