Ic Analysis Model Reduction Methods

As the IC fabrication technology advances, interconnect delay becomes a dominant factor for determining the performance of the whole chip. The fast evaluation tools for on-chip interconnects become an indispensable part of current VLSI EDA software. However, the ever-increasing signal frequency and circuit complexity together pose great challenges to interconnect modeling and simulation techniques.Model order reduction (MOR) techniques have been well investigated in the last decade to accelerate the simulation of large scale linear circuits and systems. The moment-matching based methods are the state-of-the-art techniques for MOR. There exist two important problems for the moment-matching based MOR methods, i.e., pure RLC equivalent circuit synthesis problem for the structure-preserving MOR methods, and MOR methods for interconnect circuits with large number of terminals. For these two problems, two algorithms have been proposed in this dissertation.For the pure RLC equivalent circuit synthesis problem for the structure -preserving MOR methods, a pure RLC equivalent circuit synthesis method RLCSYN is proposed in this dissertation. To guarantee pure RLC equivalent circuits can be synthesized, both the structures of input and output incidence matrices and the block structure of the circuit matrices should be preserved in the reduced-order models. In this RLCSYN method, an embeddable Input-Output structure Preserving Order Reduction (IOPOR) technique is proposed to preserve the structures of input and output incidence matrices. By combining block structure preserving MOR methods and IOPOR technique, both the block structure and the structure of the input/output matrix can be preserved. Pure RLC equivalent circuit can be synthesized from this block structure and input-output structure preserved reduced order model. Inline diagonalization and regularization techniques are specifically proposed to enhance the robustness of inductance synthesis. The pure RLC model, high modeling accuracy, passivity guaranteed property and SPICE simulation robustness make RLCSYN more applicable in interconnect analysis, either for digital IC design or mixed signal IC simulation.For the MOR of the interconnect circuits with large number of terminals, the existing methods based on input-dependent moment-matching technique either suffers from numerical problems in EKS and IEKS, or unbearable memory consumption and CPU time in EXPLIN and SAMSON. In this dissertation, a Non-Homogenous Arnoldi (NHAR) method consisting of a memory-saving and computation efficient linearization method and a partial orthogonalization Arnoldi procedure (POAR) is proposed for MOR of linear system with large number of terminals. With the proposed linearization method, the dimension of the linearized system is greately reduced. As a result, the computational cost and memory consumpation of the NHAR is remarkably low. Furthermore, since the POAR procedure is numerically stable, NHAR method can achieve higher accuracy when the reduced order increases. Compared with EKS/IEKS, NHAR tackles the numerical problems and can achieve higher accuracy, while reserving almost the same computational cost. Compared with EXPLIN and SAMSON, NHAR can significantly reduce the memory and CPU cost with almost the same accuracy.