| Semi-insulating silicon carbide (SiC) can be used for many applications related to high power device, deep submicron device, and microwave power device technology. One example is the need for semi-insulating substrates for high-power, high-frequency devices based on SiC and GaN because of their low dielectric losses in the GHz range and the high thermal conductivity. In addition, semi-insulating regions can also be applied for devices isolation or junction termination which is very important for improving the performances of devices. Due to the difficulty in the measurements of high resistance materials, it is necessary to systematically develop a series of test and characterization methods for the compensation mechanism and characteristics of semi-insulating SiC single crystal grown with the doping of vanadium. Ion implantation is a unique planar selective local doping technique available for making SiC devices. At present, there are few reports on the formation and characterization of semi-insulating SiC by vanadium ion-implantation. There are many difficulties and problems in the technique and process of ion-implantation of SiC material, such as the recovering of damage after implantation and annealing, the optimizing of annealing process, and the increasing of ions activation rate. At present, there are still diversities for the determination of the location of vanadium acceptor level in 4H-SiC. In this paper, the compensation mechanism, technology, and characteristics of the formation of semi-insulating SiC doped with vanadium are studied theoretically and experimentally. The main studies and contributions of this dissertation are as follows.(1) The fabrication and characteristics of semi-insulating SiC materials formed by several different methods are studied comprehensively. Detailed investigation of the compensation mechanism and physical properties of semi-insulating SiC doped with the vanadium in p- and n-type SiC are presented. From the analysis of theory and technique character of ion-implantation, the ion implantation range, location of peak concentration and longitudinal straggling of vanadium are calculated with the Monte Carlo simulator TRIM. The process flow of the formation of semi-insulating SiC by vanadium ion-implantation is proposed, including the determination of implantation energy and dose, annealing conditions, and mesa structure for measurements.(2) The characteristics of vanadium-implanted SiC materials in different annealing conditions are investigated. The annealing temperature of 1650℃is efficient for the recovering of damage caused by implantation. The minimum yieldχmin (10.2%) of the SiC material after annealing is closed to that of the initial material (8.6%). Significant impurity redistribution is not observed after 1650℃annealing for vanadium implanted both p- and n-type SiC. Vanadium in p-type SiC samples is relatively stable compared to in n-type samples during high temperature annealing. The test patterns on semi-insulating 4H-SiC samples were processed into mesa structure and resistivity measurements have been made. The resistivities of V-implanted layers are strongly dependent on the conduction type of initial 4H-SiC samples, and they are about 1.6×1010 ?·cm and 7.6×106 ?·cm for p- and n-type samples at room temperature, respectively. The specific contact resistance of ohmic contacts to 4H-SiC sample is investigated using linear transmission line method (TLM) structures. Comparing with the high resistivity of vanadium implanted layer (106~1010 ?·cm), the contact resistance can be neglected during current-voltage measurements. The physical mechanism in forming Nickel based ohmic contacts to n-type SiC is discussed. High temperature metallization annealing provides the enough C vacancies (VC), acting as donors, which contributes to the formation of ohmic contact. The physical mechanism in forming Al-Ti based ohmic contacts to p-type SiC is studied. It is thought that the formation of ternary Ti3SiC2 alloy during the metallization annealing is the main reason to play such an important role in converting the contact from Schottky to ohmic.(3) The surface morphology of vanadium-implanted 4H-SiC before and after annealing is investigated. At present, there are not theoretical and experimental reports on the mechanism of furrow defects on SiC surface after high-temperature annealing. From qualitative and quantitative analysis, it is found that the surface roughness is due to evaporation and re-deposition of Si species on the surface during annealing. A model is proposed to explain the observed surface roughness. The spin-coated photo-resist can be converted to graphite cap by thermal treatment. The graphite cap and high-purity crucible coated by poly-SiC is designed as the protection of SiC material during post-implantation annealing. Results show that carbon-capped 4H-SiC has a considerably lower surface roughness than surfaces annealed without the protective cap after 1650℃annealing.(4) Based on the fabrication of semi-insulating SiC layers by vanadium-implanted n-type 4H-SiC, the location of vanadium acceptor level in 4H-SiC band-gap is investigated by using temperature dependent resistance, low temperature photoluminescence (PL), and deep level transient spectroscopy (DLTS) measurements. Two acceptor levels of vanadium at EC-0.8 and EC-(1.0~1.1) eV with the electron capture cross section of 7.0×10-16 cm2 and 6.0×10-16 cm2 are obtained, respectively. This result can be used to explain the difference of resistivity between vanadium implanted p- and n-type SiC.(5) A standard test method for the compensation mechanism and characterization of semi-insulating 6H-SiC single crystal grown by vanadium doping is presented. As nitrogen is the principal shallow donor impurity in SiC by secondary ion mass spectroscopy (SIMS) measurements, semi-insulating properties in SiC are achieved by compensating nitrogen donor with the vanadium deep acceptor level. The presence of different vanadium charge states V3+ and V4+ is detected by electron paramagnetic resonance (EPR) and optical absorption measurements, which coincides with the results obtained by SIMS measurements. Both optical absorption and low temperature PL measurements reveal that the vanadium acceptor level is located at 0.62 eV below the conduction band in 6H-SiC. The main area of the wafer exhibits a good crystal quality by micro-Raman spectroscopy and X-ray diffraction (XRD) analysis. However, the polytype coexistence of 15R-SiC and 6H-SiC is observed in some parts of the periphery of the wafer. The resistivity and PL mapping measurements reveal a good homogeneity of electrical properties and vanadium doping concentration in the main area of the wafer. While the circular-shape resistivity distribution is observed with higher resistivity in the center and lower resistivity in the periphery of the wafer, and the maximum error of resistivity is 11.7%.
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