Research On Energy Estimation Of Storage Subsystem Based On On-Chip SRAM Distribution Optimization

With the advancement of semiconductor manufacturing process and IC design capability, a lot of powerful and cheap SoC chips emerge. This endows electronic terminals with unprecedented powerful processing capabilities, but it led to energy consumption problems, especially in hand-held entertainment electronic communications terminals powered by battery. The overmuch energy consumption not only shortens the power supply time of battery, but also brings some problems, like excessive heat in the system, poor stability of the system and curtate life of the system. Former research indicated that, for the embedded systems based on RISC core, in the image, video applications, the main source of energy consumption is not data access or controller, but the frequent visits to the memories, and the off-chip memory is believed to be the uppermost energy consumer, accounting for 50%-80% of the entire system. Thus, reducing energy consumption in memory subsystems becomes one of the most efficient ways to decrease the system energy consumption.This paper takes Garfield system as study object, external memory interface, on-Chip SRAM and SDRAM as objective framework for storage subsystems, put forward energy optimized method for storage subsystems by changing the memory layout, and evaluates this method with Garfield high-level software models.At frist, the paper analyses SimpleScalar simulator, compares it with Garfield system, with the markedly difference between them, such as core structure, pipeline and memory hiberarchy, indicates framework of Garfield high-level software models. Then, the paper constructs the high-level software model of Garfield systems, which contains ARM7TDMI core software model, storage subsystems software model and the energy estimation module, and builds architecture-level energy consumption evaluation framework. Simulation experiments show Garfield software model can interpret and implement arm executable program correctly, with the advantages of accurate time sequence and high simulation speed. Depending on different researcher's focus, it can accomplish information statistics and output as well. So, Garfield high-level software model becomes an energy estimation platform of storage subsystem. The paper makes a large number of intensive analysis in study of SRAM layout optimization. It takes following items into consideration, global variable, local variable, stack, furthermore, by the concept of granularity division, it divides function into instruction blocks. When analysing objects, it emphasizes the obejects' properties, such as size, number of hits, and also considers the intrinsic link among the objects and makes use of extended control flow graph(ECFG) to express the relationship among them. when calculating energy consumption income and SRAM capacity, the paper not only notices the change of object's instruction number and size, but also takes the relationship among objects into accounts. In analysis of the object memory allocation issues, paper declares it as the classic 0/1 knapsack, points out particularity and then puts forward the improved greedy algorithm. To resolve the contradiction between the small on-chip SRAM capacity and large application program, the paper dicusses the dynamic layout optimization method. It regards the time information as the each object's property and brings the concept of "time validity", this helps to resolve the problem of how to share memories for those objects which don't overlap during the life period. The method makes up some defects of former research, like circulation doesn't include condition branch, etc.The simulation experiment proves by static layout optimization, the general energy consumption decreases to 50% and the run time also decrease notablely. Meanwhile, by dynamic layout optimization technology, we can get the same effect and SPM capacity required is smaller. Hardware test validates the simulation experiment result. Paper analyses the relationship between SRAM size and energy consumption, indicates reasonable customized project in Garfield chip. Finally, after comparing the optimization effect of on-chip SPAM and Cache, paper indicates that on-chip SRAM is a better choice than the other.