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Investigation Of Special SOI Materials, Devices And SnO2 Nanostructures

Posted on:2007-09-02Degree:DoctorType:Dissertation
Country:ChinaCandidate:S H LuoFull Text:PDF
GTID:1118360185992334Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
SOI decreases the crosstalk between RF analog and digital logic circuits. So it's easy to integrate with passive elements and high resistant SOI and GPSOI enhance these advantages and attract great interests in CMOS RF integrated circuits fields. Based on the broad and deep inquiry of literatures, we study in detail the fabrication process of HRSOI using SIMOX and GPSOI with Smart-cut(?), together with the on-chip passive elements-CPWs and integrated inductors. Following results were obtained:1. High-quality HR SIMOX SOI wafers were produced by combination of high-and low-dose implantationb, breaking through the HRSOI fabrication limitation of smart-cut . Different doses of SIMOX HRSOI samples were fabricated. The resistivity of the full dose HRSOI substrate remains higher than 1 KΩ-cm; while the substrate resistivity of the low doses samples with ITOX process decreased comparing with the initial silicon wafer and the reason was proposed. Low doses of HRSOI wafers were obtained with substrate resistivity higher than 1 KΩ-cm after optimizing the fabrication process. DLTS and Pseudo-MOSFET were induced to characterize the electrical property of the HRSOI.2. Single-crystalline Si/SiO2/poly-WSix/Sub-Si structure has been successfully for the first time fabricated by a new method incorporating standard smart-cut(?) technique and high temperature reaction. Annealing at 800 ~ 1000 ℃ strengthen the bonding of the wafers and induces solid phase reaction of deposited tungsten and silicon. The SRP measurement shows annealing under higher temperature (>1000℃) will induce diffusion of tungsten into both Si substrate and the buried SiO2 layer. This contradiction makes it very important to control the composition ratio of W and Si and the condition of the solid phase reaction precisely.3. Coplanar transmission lines and integrated inductors are fabricated on different SOI substrates with standard CMOS processes. The attenuation mechanism of the CPW and inductor is analyzed.(1) The transmission loss properties of a coplanar waveguide (CPW) on SOI substrates were investigated systematically. The experimental results show the attenuation of the...
Keywords/Search Tags:HRSOI, GPSOI, SOG, passive elements, SnO2 nanostructures
PDF Full Text Request
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