Digital Cmos Process To Achieve Single-chip Local Oscillator Circuit

This thesis is about the design of local oscillator circuit for wireless communication system in standard digital CMOS technology. First, the present status and the trend of future about CMOS technology are describe in the point of RF circuit's view. The influences of the shrinkage of the device's minimum channel length to the performance of RF circuit are also introduced. Some details are also given when the CMOS technology is used as the basis of the RF design.Second, the frequency synthesizer's architectures and specifications are described. The model of PLL and phase noise are also presented briefly. In order to simulate charge pump PLL of frequency hopping systems in higher level, several methods are introduced and compared. The emphasis is on the event-driven model which can simulate the charge pump PLL quickly and efficiently. When the model is used to simulate the stability and settling time of the charge pump PLL, some improvements are made to run it faster.Third, because the realization of the circuits depend on the devices that the digital CMOS technology can provide, on-chip spiral inductor's model and design methods are analyzed. A novel LC-tank is proposed based on the standard digital CMOS process' ability. The inductor's performance is improved in its self-resonant frequency and the capacitor's area is reduced greatly. The varactor's model and design are introduced too. Some other aspect, such as active devices, interconnect, substrate, will be studied concisely.At the last, based on the knowledge of system and device, a local oscillator circuit are designed, implemented ,and tested for application of Bluetooth wireless transceiver. As the core of the circuit, a voltage controlled oscillator (VCO) using frequency doubling principle is introduced. The VCO includes two parts. The central frequency of the main VCO is half of the required local oscillating frequency. Its output frequency is doubled using the principle of "injection locking" to the required local oscillating frequency. In order to compensate the deviation of the technology, the capacitor array controlled by the digital switches is adopted in the LC tank. The inductor's performance and the area of the capacitor are improved using the method proposed in this thesis. The varactor is implemented with PMOS transistor. After the layout design, the chip is manufactured with TSMC 0.35um standard digital CMOS technology. The testing results are presented.