Design And Research On Retargetable C Compiler For Media Processors

Based on "Development of 32-bit DSP Chip in SOC and Research of Design Platform Technique" (National High Technology Research & Development Program of China), this paper is involved with the development of retargetable compiler, the optimization of object code and the verification of compiling system.According to the program structure of ANSI C, some syntax-tree-nodes are designed in front-end, including function, block, data structure, type, expression, identifier and so on. Syntax tree is divided into three levels, namely program level, function level and block level, which are useful for analysis of syntax and semantic in compiler as well as transferring syntax tree into RTL.Retargetable compiler mainly includes intermediate representation, machine description and interface technique between compiler and machine description. As target machine, MD32, is designed by ourself, the structure of retargetable compiler presented in this paper is researched. The relationship between machine description and code generation, and the technique of mapping RTL into object code by tree pattern matching are described in detail. Except for circular addressing and bit-reversed addressing, our C compiler have finished and can generate assemble code for media processor MD32.In retargetable C compiler, all instructions, including parallel instructions, are generated through instruction pattern matching, which is very difficult to generate effective parallel instructions. Meanwhile operand type required by parallel instructions is another important factor to restrict generating parallel instructions. Based on these two factors mentioned above and the difficulty to implement in C compiler, this paper proposed a method of modifying operand type by inserting instruction LW or SW at assemble level as well as instruction scheduling. Therefore, this can generate effective parallel instructions and correspondingly improve the performance and density of object code. The statistic data show that the performance of object code may be improved by 14% average while the density may be improved by 11.75% average.In the application programs of embedded system, the lifetime of many local variables usually are short-lived, and will be replaced by registers in assembler codes. Furthermore, in pipeline the values of local variables needed by dependent instructions may be directly gotten from bypassing logic, and some of them can complete all usage. With software and hardware co-design method, this paper proposes an algorithm to calculate register lifetime in programs, and the control of writing results back into RF is implemented through an enable control signal provided by instruction encoding at compile time. The results of simulation show that the average number of write operation on RF is reduced by 94% for various application programs.Based on the traditional complier testing, this paper proposes a method that introduces a reference compiler into compiler testing. By collecting dynamic data information (DDI) files in software simulator, bugs in tested compiler can be located in function level.