| This article introduces the developing history and the current situation of the automatic goal discern, and on the basis of structure of the parallel computer and neural network knowledge, it analyses the hardware and software engineering foundation that realized the real-time goal recognition system. This article also explains the operation principle and the structure characteristic of the automatic goal recognition system, designs the fictitious neural network system of many DSP parallel structure that used in fast goal discern, solves the key technology among the course of real-time goal recognition system's realization. This hardware system has fully utilized interface HPI of host computer and memory resource that DSP offers, realizes parallel structure of share memorizer mode skillfully, the whole system structure is succinct, the programming is convenient and flexible, the expanding can be strong. In this realization, the adoption of software increased its commonability and flexibility, and the adoption of hardware structure increased the speediness of discerning. Experimentation indicated that, to different goals, system had the correct discerning rate which is greater than 90%, and it could give the result of discerning within 2.8ms, this can meet the real-time character request. This hardware system absorbed SIMD and MIMD parallel structure's merit in the maximum extent, it can be used not only to realize parallel type neural network algorithm, but also to realize parallel and serial type neural network algorithm and other parallel algorithm. At the same time, it can also used as test platform to realize real-time goal recognition system algorithm in the practical project application.The thesis work includes two major parts: the hardware design and the realization of software algorithm. But, because the system is too complicated, the thesis relies mainly on the design and realization of the hardware system. The main research work of this thesis is as follows:(1) The design of gather and the pattern-recognition interface logic. Offer the bridge and tie of the information transmission between picture gather and pretreatment unit and many DSP parallel structure goal discerning unit. There is a mapping transformation from picture data source logic to host interface (HIP) logic, and considers the conversion between 5V logic and 3V logic.(2) The design of categorized DSP little system and adjudicate DSP little system. The categorized DSP little system relies on BP algorithm to finish primary discerningand classification to the goal. According to certain algorithm (for example BPalgorithm). Adjudicate DSP little system will finish the final adjudicate to lots of categorized DSP little system's output results. Each little system made up of TMS320VC5409, flash memory and power management module. Distinguish only lie in the categorized DSP little system can enable the host interface, while the adjudicate DSP little system disable the host interface. This kind of modularization design makes the parallel system structure more flexible, and may change structure according to the needs of question.(3) The design of the amalgamative logical circuit. The amalgamative logical circuit used the one that Company Lattice produced, the system programme chip could finish the merger of lots of the categorized DSP little system's output results,according to certain algorithm. And this circuit can grade join, in order to join more categorized DSP little systems.(4) The design of the amalgamative logical circuit and the interface of adjudicate DSP little system. The HIP interface of DSP is set to universal I/O port, /BIO used as handshake signal line, it can transmit merger result to the adjudicate DSP high speed. Thus it simplified the complexity of the interface circuit.(5) The design of picture data gather unit. Image processing circuit made up of several following parts: the pretreatment of the video, A/D change, the frame memory, the track window and the digital signal proc...
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