New Low-loss Silicon Thick Film Materials And Their Applications In Rf / Microwave Devices

Monolilhic microwave integrated circuit (MMIC) designs on Si substrates have become an important topic in recent years. By improving the process technologies, Si-based active devices, for example, MOSFET's and BJT's et al, demonstrate an extremely high f,f and fmax, which is sufficient for radio frequency(RF) /microwave applications. However, it is relatively difficult to realize the high-Q passive elements, especially inductor, on low resistivity Si substrates because of the native loss under the RF/microwave operation.Many approaches have been proposed to achieve better RF/microwave performance of passive elements on low-R Si substrates. The use of high-resistivity (> 3000Q.c/? silicon substrate is suggested to mimic the low-loss semi-insulating GaAs substrate, but this is an uncommon option for current silicon substrate. Etching a pit in the silicon substrate under the passive elements can remove the substrate efforts. However, the etching adds extra processing cost, and is not readily available. The use of ion implantation technology is proposed to reduce the loss of low-Si substrate through a high-resistivity surface layer by disordering the lattice sites, but its process is complicate. Other methods have been suggested to reduce the loss of low-resistivity by inserting a thick interlayer, such as a multi-layer, a thick polymide layer and a thick SiO2 layer. These solutions are basically focused on reducing low-Si substrate conduction and loss, resulting in an elimination of wave propagation in the substrate, and therefore improving the performance of the passive elements. They are accompanied by drawbacks.The paper is mainly focused on two fields. One is the formation of any thick porous silicon (PS) layers, which is content with 1C process. The other is the low-loss performance of passive elements fabricated on PS/ oxidized porous silicon (OPS) inter-layers under microwave operation. Our research results are listed in the following items.The use of PS/OPS was proposed as a low-loss and low-dielectric-constant inter-layers for passive elements in the (MMIC). A complete process flow has been developed for PS thick layers up to SOOum.The formula of the velocity for PS growth was derived, and was in fairly good agreement with the experimental data in the errors.The solution of H2O2 is first used to post-treat thick porous silicon (PS) layers. The prepared thick porous silicon layer as the cathode is applied about 10mA/cm2 current in mixture of ethanol, HF and HiCb solutions, which is expected to improve the stability and the smoothness of the surface and the mechanical property of the porous silicon thick layers. After analysis of the XRD data, an obvious small peak was observed at 29 = 32.62? The experimental results showed that the improved stabilization of the porous silicon layers was due to the formation of SiO2 (1103) structure in the internal surface.Successfully obtaining PS layers thickness up to SOOum by anodic electro-chemical etching, its resistivity is up to 105fi.cm. The SEM images show significantly improved smoothness on surface of porous silicon layers, and the micro-inter-distance is about 20nm.The loss of coplanar wave-guides (CPWs) on PS/OPS layers with thickness about 10, and 70um respectively on low-resisitivity (O.Olflcm) Si has been studied, which are expected to increase the substrate resistivity and then to reduce its effective dielectric loss under the microwave operation. A significantly improved microwave performance on low-R Si substrates has been demonstrated by measuring the microwave characteristics of CPWs fabricated on the Si substrates with thick oxidized porous silicon surface layers, and the CPWs insertion losses are only 7dB/cm. The low-loss distributed MEMS phase shifter fabricated on PS layers is studied, but how to achieve better performance needs further works. Thick PS/OPS layers will be very attractive inter-layers for silicon 1C applications.