Study Of Low-power Design Methodology For Digital Circuits

In the last few years, with the explosive growth in the portable electronics market, the emphasis on VLSI and system design is shifting away from high speed to low power. This adds another degree of freedom and complexity to the design process as well as area and speed.In this thesis, the history of low power technology is simply retrospect and the state-of-the-art development is introduced. Based on the study of power resource, power estimation and various common low power methods, many power optimization strategies are presented in this thesis. The main works and creative methods are as follows:1. The character of threshold voltage in VLSI circuit is analyzed. It can make a serious effect on power dissipation and performance. An algorithm based on partition is designed to choose the most favorable working voltage and threshold. It can reduce power dissipation dramatically. However, the leakage power severely increases because of the low threshold, so a simulated annealing algorithm is presented to adjust threshold in non-critical paths, while the threshold in critical path is still kept low to increase performance. This method can decrease leakage power by 100 times without speed penalty.2. A gate resizing algorithm based on genetic is brought forward. Nodes in non-critical path can be powered by a low supply voltage or resizing. Two greedy algorithms CVS and MIWS have been taken to resolve this problem, but both them lack of global view to obtain the maximum power reduction. In this thesis, a genetic algorithm is exploiting to seek a optical solution. Each gate select a proper voltage and size. Experimental results show that the average power reduction is as highas 20%.3. Avoiding waste is an important strategy in Low power design, a task-driven energy-efficient methodology has been explored to minimize power in microprocessors. A Genetic Algorithm was applied to select a favorable voltage for each task base on the time limit of task queue. By introduce to this system, about 40-50% power dissipation was cut on average.4. A novel dynamic power management is presented based on predictive and timeout policies. Online idle period is predicted according to previous idle period and previous prediction. In order to cope with errors aroused by a long sudden idle period, an adaptive coefficient to avoid overestimate the online idle period has been provided. On the other hand, timeout policy is taken to reclaim shutdown in the underestimate situation. Experimental results show that this algorithm outperforms other advanced dynamic power management policies because of less wrong shutdown times and wrong waiting times.