| In order to recur marine accident, the voyage data recorder is required to record no less than 3 radar images per second.To record radar images efficiently, they must be compressed, due to limited capacity of storage medium.As the latest still image compression standard, the JPEG2000 standard has excellent performance, and it has been widely used in many applications;however, it is not suitable for radar images compression in the voyage data recorder due to its computational complexity and other disadvantages.In this thesis some modules of JPEG2000 algorithm have been improved according to properties of radar images in voyage data recorder and VLSI structure has also been designed which is suitable for radar images. Based on modified algorithms and designed VLSI structure, a radar image recorder card is finally designed.Detailed researches are as follows:Firstly, according to the properties of radar images,improvements have been obtained for DC level shifting module and the quantization module of the JPEG2000 standard.It is based on the conclusion that the radar images don't need DC level shifting, which reduces the computational complexity of the encoding process, saves hardware cost and improves encoding performance. According to visual characteristics of human eyes,a mathematical model is established,which formulates the relationship between stream lengths of color radar images and quantization steps of tri-color components.By this mathematical model,the optimal scaling relationship of quantization steps of tri-color components is obtained. In order to facilitate hardware implementation, a method is proposed that the scaling factor among quantization steps of tri-color components is an integer of power of 2.Secondly, according to the recorded radar image frames in practice, three VLSI architectures for 2D-DWT are designed.The first VLSI architecture of 2D-DWT is based on time-difference and its processing throughput is 2 per clock cycle.The second VLSI architecture of 2D-DWT is based on SISO,and its processing throughput is 1 per clock cycle.As compared with other VLSI architectures with similar throughput, the proposed architectures have better performance in hardware cost.To solve the problem that floating-point lifting coefficients for 9/7 wavelet are difficult to be implemented in hardware, a new method is proposed in which wavelet filter coefficients are rationalized on the basis of genetic algorithm.This method reduces the computational complexity and can be easily implemented by hardware.A new method is also proposed to calculate the integer digit for multi-level discrete wavelet transform (DWT),which can determine the optimal integer width of DWT coefficients.Thirdly, an embedded block coding architecture is designed for radar image compression.The bit-plane coding in the embedded block coding is based on bit operation which consumes a lot of time in the implementation of image coding. Thus the design and implementation of the bit-plane coding architecture are key issues to improve the coding speed.According to the research on the existing VLSI architecture of the bit-plane coding, a new VLSI architecture is proposed in which stripe-column and coding are both implemented in parallel.In this architecture three coding operations can be completed for the stripe-column per clock cycle, and its processing throughput is 4 per clock cycle.At the same time, this architecture saves internal memory resources.Finally, a radar image recording card is designed.According to the parallel process architecture designed previously, the radar image recording card is designed based on XC3S2000 FPGA from Xilinx Corporation. It has been tested according to the test standard of radar images in "voyage data recorder test guide" issued by CCS.The testing results show that the recording card satisfy international standard.
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