Compiling Optimization Technique Research For Dynamic Dual-mode Multi-level Parallel Architecture

The rapid development of wireless communication and video image processing has brought higher performance requirements to Digital Signal Processor(DSP). DSP has powerful data processing capability, good programmability and flexibility. Dynamic dualmode multi-level parallel DSP(DDMP-DSP) is a high-performance floating-point DSP for wireless communication and video image processing. DDMP-DSP has dynamic dualmode multi-level parallel architecture, which supports instruction level parallelism based on Very Long Instruction Word(VLIW), data level parallelism based on Single Instruction Multiple Data(SIMD) and task level parallelism based on dynamic dual-mode switching.Software tool chain is very important to the usage and performance of new architecture. In wireless communication and video image processing applications, with the increase of algorithm complexity, the application development becomes more complex.Manual optimization can not fulfill the requirements of application development. The high level language compiling optimization becomes necessary, which brings higher requirements to the design and development of high level language compiler. The performance of dynamic dual-mode multi-level parallel architecture largely depends on the compiler.Traditional compiling optimization techniques for DSP can not take full advantage of the characteristics of DDMP-DSP architecture and cannot develop its performance.This dissertation studies the compiling optimization techniques for DDMP-DSP architecture. For the three-level parallelization, this dissertation sets up execution model,programming model and cost model. It designs and implements three compiling optimization techniques, including scheduling optimization, data reorganization and parallel loop optimization, which can support the architecture and instruction set of DDMP-DSP. The major contributions and innovations can be summarized as follows:1) Based on the architecture of DDMP-DSP,this dissertation proposes a Dual-mode multi-level parallel execution model(DDMPEM), which supports dynamic VLIW,wide SIMD and dual-mode switching. This dissertation designs Kernel based programming model(KBPM). Programmers can develop applications conveniently by using KBPM and the compiler can work efficiently with the support to KBPM.This dissertation proposes a Dual-mode multi-level parallel cost model(MPCM). It takes instruction level parallelism, data level parallelism and task level parallelism into consideration It is used to direct the compiling optimizing techniques.2) This dissertation proposes Dual-mode optimal scheduling technique(DMCOS) supporting task level parallelization. Vector unit(VU) and Scalar unit(SU) in DDMPDSP can work serially in Tightly coupled Mode(TCM), they can also work in parallel in Loosely coupled Mode(LCM). DMCOS can decide the switching opportunity and support the dynamic switching between TCM and LCM. DMCOS does Independent Dual-mode Scheduling to Dual-mode Code field(DMC) in KBPM, or DMCOS does Flow Scheduling and Dual-mode Switching Scheduling to DMC in KBPM based on Dual-mode Switching Cost Model. With DMCOS, the task level parallelism in applications can be explored. It can convert high level language programs to the code which can satisfy the requirements of DDMPEM. DMCOS can make full use of the advantages of dynamic dual-mode architecture and explore task level parallelism.3) This dissertation proposes Data reorganization compiling optimization technique for wide SIMD(DRWS) supporting data level parallelization. VU in DDMP-DSP includes a set of isomorphic Vector Elements(VE) and supports wide SIMD. DRWS includes three modules:Data reorganization based on multi-modulo(DRMM) module, Data reorganization for wide vector filling(DRWF) module and Data reorganization for branch(DRB) module. Three modules manipulate data reorganization in various cases. DRWS can organize data reasonably and efficiently. It can support flexible data reorganization. The number of VE can be well matched and the computing resource of VU can be fully used in SIMDization.4) This dissertation proposes Multi-level loop optimization compiling technique(MLOP)supporting data level parallelization and instruction level parallelization. MLOP combines polyhedron optimization, SIMDization, VLIW and runtime optimization.It includes polyhedron optimization module, S-â…¡ SIMDization module, VLIW module and Runtime optimization module. MLOP uses the method similar to iterative compilation to do compiling optimization. It can integrate a variety of factors, select appropriate loop unrolling factor and perform loop optimization. MLOP can explore data level parallelism and instruction level parallelism in applications efficiently.