High Performance Through-Silicon-Viain3-D Interconnection

Traditional Integrated circuits are facing great challenges in constant reduction of the transistor feature size, but novel 3D integration based on Through-Silicon-Via(TSV) technology shows a feasible solution achieving a high-density IC integration. In its evolution, several potential electrical and thermal issues emerge. This work will address the TSV performance issues due to the structure design such as large parasite capacitance and thermal-stress failure, and propose several novel TSV structures.Upon the theoretical calculation and finite element analysis simulation, we concluded:(1) TSV parasite capacitance is the dominant factor on interconnection delay and power consumption;(2) thermal stress in TSV can be released by stress buffer layer. Therefore this work presented new material and improved structure designs to break through the performance barrier, and we successfully enhanced TSV interconnection performances in terms of reduced signal delay, cross talk and loss, and its mechanical stability by lowering inner stress to suppress failure risk. Since polymers and air feature low dielectric constants and are capable of buffering stress, this work proposed two novel TSV interconnection approaches: polymer-isolating and air-gap-isolating TSVs. Selected upon material properties and process parameters, poly(propylene carbonate)(PPC) and benzocylcobutene(BCB) are used in polymer-isolating approach, and air-gap isolating approach is fabricated by sacrificial layer releasing. All structures above were successfully fabricated upon a comprehensive study on key steps such as polymer sidewall coating and sacrificial layer releasing.First, by direct spin-coating and deep trench filling, we achieved 46:1 and 24:1 thin polymer sidewall surrounding coatings, respectively. Based on direct spin-coating, PPC liner TSVs were fabricated, showing reduced parasite capacitors(95 f F in accumulation region) but a weak thermal-mechanical stability.BCB liner TSVs were then fabricated by deep trench filling. BCB can effectively reduce parasite capacitors(53 fF in accumulation region), and maintain electrical stability with less than 50% C–V hysteresisvariation at higher temperatures which indicates a great suppression of the mobile charges. BCB liner can reduce the substrate stress and buffer the thermal structural stressvia thermal shock and thermal stress analysis.BCB liner TSVs are able to tolerant shock impacts up to 20 G, and maintain good electrical properties in humidity environments.Those above conclude the great performances of BCB liner TSVs in thermal, mechanical and(humidity) tests.Finally, 1 um and 2.5 um-thick air-gap TSVs were fabricated using polymers as the sacrificial layers. Air can sufficiently decrease parasite capacitors(25 fF in accumulation region) and the leakage current(0.13 pA at 30 V). By introducing the SiO2 thin layer, air-gap TSVs showed stable electrical performances and little C–V hysteresis in a wide range of temperature settings. After the thermal shock test, TSV electrical properties showed little shift, and TSV induced stress descreases with higher temperature, which indicated a good stress buffering effect from air gap. These TSVs have good resistances to transient impacts but normal to continuous ones due to suspended structures. The addition of SiO2 thin liners to air gap boundaries improved TSV electrical stability.