Application-driven Multi-processor System-on-chip Energy Optimization Techniques

In recent years, integrated circuits (IC) cannot meet people’s requirements by using better manufactory process, and then IC designers developed high integration-density and high complexity system-on-chip (SoC) to cope with this pressure. Multi-processor system-on-chips are becoming major and popular IC solutions for embedded systems, but their energy consumption is a cruel problem because of their high density and complexity, and it’s a challenge to designers. In the SoC design flow, designers, on one hand, should evaluate the energy consumption of each module and adjust the architecture according to the evaluation results. On the other hand, they should adopt various energy efficient strategies in a SoC, and implement the corresponding hardware and software to improve energy efficiency.Piles of works focus on low power techniques, such as dynamic voltage & frequency scaling (DVFS) and clock gating. However, low power doesn’t mean energy efficient. Energy efficiency reflects the work that’s done by consuming a unit of energy. Usually, low power techniques make the running time of a task longer, and it will lower energy efficiency if the task’s execution time is longer enough. So, we should taken execution into account when considering energy efficiency, and we should also do quantitative energy analysis for each module. In the second palce, low power techniques are always based on low level circuit, such at RTL or Gate level, which are late design phases in a SoC design flow. Along with IC’s development cycle lengthens with the complexity upgrading, energy evaluations and optimizations at RTL/gate level are more time consumping. For these two reasons, it is too late for architecture adjustment if the result didn’t meet original requirement, and the adjustment should be very difficult. So, we need develop energy evaluation and optimization methods at early stages of the SoC design flow.Hence, we deeply study the energy efficient techniques of MPSoCs in this paper. As each MPSoC sub-system has its own characters, and we can use these characters, localize MPSoC’s complex problem as a whole, and develop suitable low energy strategies and techniques for subsystems. Meanwhile, we explore low energy techniques for both dynamic and static energy for each subsystem. The research work covers the following three aspects:1) Energy evaluation and optimization techniques for CPU subsystems. In order to evaluate energy consumption at early stage, firstly we propose a refined instruction-level energy model for CPUs, and present a profiling and annotation combined method for energy evaluation. In our strategy, MPSoC is modeling at virtual architecture (VA) level and transaction accurate (TA) level, which makes the evaluation process fast and accurate. GNU gcov is employed to profile the execution statistics of the given C code during native simulation at VA level, and runtime energy analysis is supported. Then the result of VA level is annotated to TA level model, in which communication latency is refined and enables more accurate execution time estimation. Finally, we analysis the evaluation results, put forward an architecture with accelerator by H.264/AVC decoding drivened MPSoC’s CPU subsystem. Some high energy consuming logics have been implemented with hardware accelerator, such motion compensation and intra prediction.2) Energy optimization techniques for memory subsystems. On-chip shared Cache plays an important role in memory subsystem, and contributes a large portion of MPSoC’s energy consumption. An access adaptive and thread aware cache partition scheme is proposed in the research. In the scheme, specific to data type of multi-core, we propose that cache regions can be divided into shared and private, and accessing type is distinguished with data type. Then we present a hardware/software architecture for supporting cache partition, in which the accessing type, code size and data size are taken into account. Cache memory is reasonablely allocated and used through partitioning. Additionally, we take thread number into consideration. By integer linear programming modeling and solving, the partition algorithm in the work can achieve best energy consumption and get the corresponding cache allocation for each CPU core.3) Energy optimization techniques for communication subsystems. In order to avoid being affected by task mapping, thread partitioning and scheduling, this research proposes a method combining mes sage aggregation and communication pipelining techniques. In this method, message aggregation technique can reduce communication times then to reduce energy consumed by activating communication. Communication pipelining technique can reduce the consuming energy while waiting for communication, by hidden the communication time behind computation time. Further, a quantitative analysis for message aggregation and communication pipeline is done in this work. By integer linear programming modeling and solving, we get best arrangement for energy saving based on the proposed message aggregation technique and communication technique. Last but not least, aiming at cache coherence protocol among symmetric multi-cores, we propose an efficient snooping filtering scheme. In this technique, snooping requests are analyzed carefully, and the redundant snoops are filtered. By doing these, congestion of communication subsystem is reduced, and then its energy is further reduced.