| As demands accelerate for extreme miniaturization, higher bandwidths and lower power,3D integrated circuit (3D IC) technology complements conventional transistor scaling to enable designers to achieve higher levels of integration by allowing multiple die to be stacked vertically, or in a side-by-side "2.5D" configuration on a silicon interposer.3D ICs promise "more than Moore" integration by using through-silicon via (TSV) technology and conventional flip-chip packaging. A TSV with copper filled commonly is a vertical electrical connection passing through a silicon die. Compared to a wire-bonded SiP, TSVs offer reduced RLC parasitics, better performance, more power savings, and a denser implementation. Compared to a silicon interposer approach, a vertical3D die stack offers a higher level of integration, smaller form factor, and faster design cycle. While there is great interest in this emerging technology, it is still in its early phases. Standard definitions are lacking, the supply chain ecosystem is still in flux, and design, verification and test challenges need to be resolved. From the EDA design perspective, the good news is that extensive retooling is not needed for3D ICs. However, new capabilities centered on TSV are needed in such areas as architectural analysis, floorplanning, place and route, thermal analysis, timing, signal integrity, parasitic extraction, IC/package co-design, and test. Some of these capabilities are available today, and others are under development. In this dissertation, we research on3D IC TSV assignment and Flip-Chip routing problems in the procedure of IC physical design.For the3D IC TSV assignment problem, a practical model for TSV assignment of3D nets and an integrated algorithm assignment are proposed. We first proved that the general pre-placed3D IC TSV assignment problem with more than two dies is NP-complete. Subsequently, an integrated algorithm that combines shortest path search, bipartite matching, min-cost max-flow calculation and post processing is developed and well described. The first step is to find the shortest path of each net and get the lower bound of the total assignment weight. This initial solution is potentially illegal because multiple nets may share the same TSVs or micro bumps. Bipartite matching and min-cost max-flow calculation are then applied to split nets that share the same TSVs and a feasible assignment solution is derived. Finally, a post processing step can be optionally carried out to further optimize the TSV assignment. The proposed algorithm is also extended to handle multi-pin3D nets and some heuristic speedup strategies are introduced in the steps of shortest path search and min-cost max-flow calculation. Experimental results using actual testing silicon data demonstrated that our flow achieved good quality of results with reasonable running time when compared to existing works.For the flip-chip routing problem, a solution for global routing and track assignment of flip-chip I/O nets is presented. We use the Voronoi diagram theory to construct the global routing channel graph. The channel’s routing capacity is calculated by estimating the routing direction and width of the channel. A flow network is then constructed on top of the channel graph to find a globally optimal routing solution by min-cost max-flow calculation. A track assignment algorithm is then used to refine the global routing solution while avoiding wire crossing. Some straight-forward improvement extended from the proposed routing algorithm is also proposed and discussed. Experimental results based on actual designs from industry demonstrate that our algorithm and implementation improves routability and wirelength when compared to the existing implementation in an EDA commercial tool.
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