Keyword [VLSI] Result: 181 - 200 | Page: 10 of 10 181.  VLSI Design For The Key Module Of MPEG2 Decoder 182.  VLSI Design Of Full-Search Block-Matching Full-Pel Motion Estimation For H.264 183.  A High Parallel VLSI Architecture Design For H.264 Fractional Motion Estimation 184.  The VLSI Implementation Of MQ Arithmetic Decoder 185.  The Research On VLSI Routing Base On Ant Colony Algorithm Associated With Artificial Immune Algorithm 186.  VLSI Design And Implementation Of Bit-plane Coder In JPEG2000 187.  Application Of Lifting Wavelet Transform And Its Hardware Implementation 188.  A Fully Parallel Decoding Architecture Of Turbo Code And Its VLSI Implementation 189.  A VLSI Implementation Of EBCOT Encoder For JPEG2000 190.  VLSI Design Of EBCOT T2 Encoder 191.  Research On Partition Algorithms Applied In VLSI Domain 192.  A Hardware Implementation Of Lossless Data Compression Based On LZW Algorithm 193.  Design And Implementation Of VLSI Architecture For Lifting-based Discrete Wavelet Transform 194.  Research And Design For A Speech Recognition Co-processor 195.  Research On VLSI Net Routing Based On Tabu-ant Colonies System 196.  OFDM Based Chip Design Of Receiver Baseband 197.  Lifetime Modeling And Characteristics Of TDDB In VLSI Copper Interconnection 198.  The Design And VLSI Implementation Of Digital Filter Based On Oversampling 199.  Optimized Motion Compensation VLSI Implementation For H.264/AVC Decoding 200.  VLSI Design And Softcore Realization On Bit-plane Coding In JPEG2000   <<First  <Prev  Next>  Last>>  Jump to

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