Analytical Modeling Of Multicore Shared Cache Behavior And Its Application

To mitigate the ever worsening “Power wall” and “Memory wall” problems,multi-core architectures with multi-level cache hierarchies have been widely used in modern processors.However,the complexity of the architectures makes the modeling of shared cache extremely complex.First,sharing and conflict caused by the concurrent threads running on different cores are hard to be quantified.Second,the “filter effects” resulted by the multi-level cache and the coherence misses caused by multi-core,which make the modeling of cache behavior extremely difficult.In this thesis,we propose a data-sharing aware and scalable analytical model for estimating the miss rates of the downstream shared cache in a multi-core environment.The data sharing effects is quantified by using probability derivations based on the information of access address distributions for each core.Moreover,the proposed model also be scalably integrated with upstream cache models with the consideration of multi-core private cache coherent effect,which aviods the time-consuming simulations of the cache architecture.The proposed model is validated against Gem5 simulation results under 13 benchmarks from PARSEC 2.1benchmark suites.The average absolute error is less than 2% for all configurations by comparing the L2 cache miss rates with the results from Gem5 under 8 hardware configurations including dual-core and quadcore architectures.After integrated with upstream model,the overall average absolute error is 8.03% in 4hardware configurations.After verifying the accuracy of the model,the proposed model is used to explore the design space of the cache architectures in multi-core multi-level cache processors.The evaluation explores the missing rates of shared cache under 57 kinds of cache hardware configurations.The result is used to guide the parameter selection of the cache hardware configuration.