The Dual-core Processor Of Multi-level Cache

The work in this dissertation based on National 05' project entitled "Application Specified High Performance Microprocessor (Longtium R2)". The purpose of the project is to design an embedded 32-bit microprocessor, whose instruction set is compatible with PowerPC, by studying RISC architecture and exploring design methodology.The author is responsible for the design and verification of MMU, L1 cache and L2 cache of "Longtium R2" microprocessor, and then performs in-depth research on the cache hierarchy and consistency of the CMP (Chip Multiprocessor). Proposed the L2 cache design of "Longtium D2" that is a dual core microprocessor.The research work of this paper mainly includes:1. Performed systematic research on Memory Management and cache control of the High Performance Microprocessor. Then the Memory Management Unit, L1 Cache and L2 cache which are compatible with PowerPC instruction set are designed and implemented. The simulation results and analysis prove that it is fully compatible with PowerPC750 in function.2. Based on the successful implementation of "Longtium R2", this paper researched the CMP architecture, analyzed the cache hierarchy and interconnection of the dual core processor and proposed the cooperative cache, which is suitable for "Longtium D2" microprocessor.3. Studied the current hardware solution to resolve the cache consistency, afteranalyzed and compared, the cache consistency protocol——MESI protocol,which is suitable for "Longtium D2" microprocessor is designed.4. Completed the design of the "Longtium D2" L2 cache, including the architecture design, hardware support, interconnection mechanism and the state machine of main controller etc. The cache design support the global and "shared" management of the cooperative cache and support communication between L2 cache.