DSOI Parasitic Bipolar Effect And Back Gate Modulation Effect

With the development of integrated circuits,the demand for circuit and chip performance and low power consumption is increasing,which requires the improvement of device performance.In order to achieve high performance and low leakage of the device,device designers have been pursuing: high on-state current,low subthreshold swing,and low leakage current.However,with the decrease of device process size,there are some leakage mechanisms that must be considered in short channel devices,which will seriously affect the leakage current.The parasitic bipolar effect(PBE)can not be ignored in small size SOI devices.In some extreme environments,the performance and power consumption of the device are severely affected,which places high requirements on the reliability of the device.In this paper,a new type of DSOI device is studied from the following aspects:the dominant mechanism of parasitic bipolar effect,the influence of voltage and temperature,the characterization of gain,the circuit application and so on.The main research works are as follows:1)Based on the test of transfer characteristic curve Double Silicon-on-insulator N type MOSFET(DSOI NMOS)with a channel length of 0.5 ?m at different temperatures and drain voltages,the leakage current changes with temperature and drain voltage are analyzed.According to the experimental data and device parameters,a TCAD simulation model is established,and the leakage current amplification mechanism is analyzed through the simulation results,and the dominant mechanism of the parasitic bipolar effect under different conditions is determined.In addition,by applying a negative voltage bias to the back gate of DSOI NMOS,it is found that the leakage current can be effectively reduced.Sentaurus TCAD simulation is used to analyze its modulation mechanism.2)The influence of the coupling of the parasitic bipolar effect and the self-heating effect on the on-state current is considered.Firstly,a TCAD simulation model is established based on experimental data,and the mechanism of the self-heating effect of DSOI NMOS is analyzed.Considering the influence of voltage on the self-heating effect,it is found that the drain voltage and gate voltage will increase the self-heating effect of DSOI NMOS.The coupling mechanism of parasitic bipolar effect and selfheating effect under different voltage and temperature is studied by simulating the output characteristic curve of the device.3)Based on experimental test and TCAD simulation,the influence of parasitic bipolar effect in DSOI circuit at high temperature on performance and power consumption is studied,and it is found that the parasitic bipolar effect caused by NMOS at high temperature increases the leakage power consumption in the circuit.The output voltage of the converter and the stored data in the SRAM will cause soft errors.And applying negative back-gate bias on DSOI NMOS can effectively reduce power consumption and restore data.In addition,temperature simulations were performed on the static noise margin(SNM)of SRAM,and it was found that temperature would reduce the SNM.Using the independent back-gate characteristics of DSOI,the optimal back gate bias strategy of DSOI SRAM was proposed to effectively increase the SNM and ptimize circuit performance.