Research And Implementation Of The Digital Model Based On The PowerPC Architecture

With the rapid development of the Internet of things industry,embedded system has gradually become one of the most popular technologies.The application-based So C chip and embedded program are the emphases of embedded technology in the future.Embedded systems are widely used in communications,national defense,Aeronautics and Astronautics,industrial control,etc.In these areas,Power PC embedded chip has become the main force with its strong comprehensive performance and the characteristics of open source instruction set architecture.Due to the complex structure and high requirements of high-end embedded computer,its development process needs to be studied and demonstrated repeatedly,so the development of embedded software is difficult to start before hardware delivery.In addition,the actual Power PC chip is expensive,and the development cost based on the real hardware environment is very high.Aiming at the above problems,based on the existing technology research,this paper selects the current mainstream QEMU virtualization platform to carry out digital modeling and implementation of the high-performance embedded development board based on Power PC architecture.Research on embedded virtualization technology in Power PC architecture is of great significance for localization of high-end embedded chips.The main research work of this paper is as follows:Firstly,based on the existing virtualization technologies,this paper analyzes the application fields and advantages and disadvantages of the current mainstream virtualization platforms,and selects QEMU as the virtualization platform in this paper.Based on the application scenarios and functions of Power PC high-performance embedded development board,the functional requirements and performance requirements of Power PC digital model are analyzed.On the basis of previous studies,the digital model is divided into modules and functional planning,so as to complete the overall scheme and the design of each module scheme.Secondly,according to the requirement analysis and design scheme,the framework of the whole digital model is constructed.Since the embedded processor and instruction set based on Power PC architecture in QEMU are not perfect,it is necessary to model and realize the CPU core structure and Power PC instruction set translation by combining QEMU operation mechanism and Power PC programming framework.The operation of the digital model also needs the support of memory devices and interrupt controllers,timers,serial ports and other peripheral devices.According to the design requirements of each module,the virtual realization of memory devices and peripheral devices required by the digital model is completed.Finally,the system development and test environment was built by using the crosscompilation tool chain.According to the hardware manual of the digital model,appropriate methods were adopted for different modules to complete the functional test of the processor,instruction set,memory device and various peripheral devices of the Power PC digital model.Based on the completed digitized model,write a test case to invoke the function of the timer to keep the instruction execution state,collect the model running data to complete the performance test of the digitized model.This paper finally uses the QEMU virtualization platform to implement the digital model of the high-performance embedded development board based on the Power PC architecture.After the function test and performance test,the digital model meets the function and performance requirements and can be used for embedded software development.By building Power PC digital model,the time and cost of developing high-end embedded system can be saved.And through the construction of Power PC digital model in this paper,the implementation model of QEMU applied to Power PC embedded processor is improved.