Dynamic Binary Translation Modeling And Parallelization Research

With the development of domestic processors, in particular the development of the domestic multi-core processors, how to solve software migration has become a key factor of the processor market-oriented application. The compatibility of binary software limits software migration for different hardware architectures and hinders the development of new architecture. As a cross-platform dynamic com-pilation technology, dynamic binary translation provides a possible software way to solve binary code compatibility among different architectures. It also provides a new direction for dynamic optimization and virtualization technology.For the high complexity of modern hardware architecture, there are many tremendous differences among different architecture. In order to make up hard-ware differences, dynamic binary translation takes a lot of overhead to simulate the differences. As a result, the performance is much lower than the performance of local program. The low performance hinders widespread application of dynamic binary translation technology. How to improve the performance of dynamic binary translation system is the most important research issues. Because the multi-core platform has rich computing resources, how to parallelize the traditional dynamic binary translation is a hot topic of current research work.In this dissertation, we conclude a "translation-execution-lookup" model for dynamic binary translation, which is based on the research of Loongson dy-namic binary translation system and other run-time systems. According to this model, the dynamic binary translation system can be divided into three mod-ules:translation module, execution module and lookup module. The content of this dissertation focuses on the three main modules. The main research content includes the following aspects:1, Concluded a "translation-execution-lookup" model for dynamic binary translation. Based on the analysis of a lot of run-time systems, this dissertation concludes a "translation-execution-lookup" model for dynamic binary transla-tion. The dynamic binary translation system can be divided into three modules: translation module, execution module and lookup module.2, Proposed a target address of indirect branch quick lookup algorithm. In the lookup module, the indirect branch instruction is a bottleneck of the dynamic binary translation. According to a analysis of the distribution of the target address of the indirect branch, this dissertation proposes a local buffer to quickly find the target address of indirect branch。This algorithm can reduce the number context switching between translation module and execution module.3, Improved the design of the multi-thread translation model for dynamic binary translation. In the translation module, this dissertation analyzes and com-pares the advantages and disadvantages of existing multi-thread translation model for dynamic binary translation. It proposes the stack-based prediction algorith-m and uses a wait-queue algorithm to manage the multiple translation threads. It also proposes a copy-base method to improve the locality of the distribut-ed code cache. The improved multi-thread translation model provides a basis of multi-thread dynamic optimization and parallelize the traditional dynamic binary translation.4, Proposed an all registers mapping algorithm for register simulation. In the execution module, the register simulation has a critical effect of the expansion rate of translation code. Integrating the memory-based and direct mapping simulation method, this dissertation proposes an all registers mapping algorithm for register simulation. It also simplifies the intermediate code translation rules based on this algorithm.5, Designed and implemented a simulation method for atomic instruction for Loongson CPU. In the execution module, we implement the thread-level paral-lelization of the independent computing unit. Based on existing parallel multi-core simulators, this dissertation design and implement thread-level parallelization of the multi-core simulator for the Loongson platform. For the simulation of the virtual memory mechanism and atomic instruction, it propose a special method for Loongson CPU.