Design and evaluation of a hierarchical bus multiprocessor

This thesis describes the design and evaluation of the protocol and controllers which maintain memory coherence in a hierarchical bus multiprocessor. The architecture studied represents a natural step in the evolution of bus-based shared memory multiprocessors. Extending the scalability of these machines beyond the current single bus limit of 20 processors preserves the inherent advantages and familiarity of the bus interconnect and the shared memory programming paradigm.; Cache memory is vitally important in bus-based multiprocessors for reducing memory latency and for conserving bus bandwidth. A new cache coherence protocol, designed for hierarchical buses, is used to solve the attendant problem of cache and memory coherence. A design and debugging tool based on Petri net simulation was developed to evaluate detailed models of the controllers implementing the cache coherence protocol. The Petri net simulator is completely general, but is particularly adept at representing concurrency and synchronization; a necessity for modeling parallel computer architectures.; Performance evaluation of the architecture under study was accomplished with object-oriented discrete event simulation. The overall performance of a bus-based multiprocessor is heavily dependent on the performance of cache memory, since the system buses are potential bottlenecks. Two simulation models were developed. The first, a purely probabilistic model, can be used to quickly explore a wide range of system configurations and parameters. A second, more detailed, trace-driven model accurately represents the activities and state of a single cluster of processors. Trace-driven simulation is necessary in evaluating the hierarchical bus multiprocessor since the performance of cache memory is highly dependent on the pattern of memory accesses. A method of gathering architecture independent multiprocessor address traces on a conventional uniprocessor was developed to facilitate trace-driven simulation.; Simulation indicates the hierarchical bus architecture increases the ultimate size of bus-based multiprocessors by nearly an order of magnitude to approximately 200 processors. Detailed Petri net modeling and simulation suggests the feasibility of the controllers and the correctness of the cache coherence protocol.