| In this thesis, we target the analysis and design of power distribution networks in VLSI circuits. In modern and future designs, power distribution networks are becoming performance limiting factors. Voltage drop on the power grids may cause functional failures or slow down the chip so that it is impossible to meet timing requirements. On the other hand, high supply current's flowing through the power and ground grids may cause electromigration failures. Thus, it is critical to analyze power distribution networks for severe voltage drop and electromigration failures.; Current estimation is a critical component for power grid analysis. In this thesis, we present some of the existing techniques for current estimation and then propose some enhancements to improve the estimation over multiple cycles. Another critical component of power grid analysis is the efficient modeling and simulation of power grids. The challenge in simulating the power grids of modern designs relates to the huge size of these power grids, typically in the millions of nodes. Existing simulation methods are incapable of simulating such huge systems; thus, there is a clear need for new and efficient simulation techniques. One such technique is proposed in this thesis and the results verify its usefulness and practicality. The technique is inspired by the multigrid approach, which is a common approach for solving partial differential equations.; After discussing the requirements for efficient analysis of the power grids, we discuss one design technique which targets a correct-by-construction placement of power hungry buffers. In particular, we tackle the problem of I/O buffer placement in area-array, also referred to as flip-chip, designs since I/Os are typically power hungry buffers. The problem is aggravated by the fact that in area-array designs, I/Os can be placed anywhere on the chip and are not limited to the periphery. We model the problem mathematically as an integer linear programming (ILP) problem. Then, we propose a greedy heuristic which places the I/O buffers while satisfying a set of user-specified drop thresholds. The proposed greedy heuristic also avoids the exponential complexity of the ILP solution. The results reported on real ASIC designs illustrate the practicality of the algorithm.; Finally, we conclude with a summary of our research in addition to future research directions. |
