Layout effects modeling for analog circuits design automation

Deep sub-micron (DSM) integration brings about aggressive technology scaling to accommodate large and high-speed systems onto a single chip. The integration and migration of mixed-signal systems to smaller process nodes have shortened the traditional analog circuit design cycle and increases performance influence due to parasitic coupling. Current analog optimization tools demonstrate promising results at the schematic netlist-level, but inherited layout effects are excluded until the physical design is completed. If coupling effects are ignored or poorly modeled, schematic optimization results are no longer accurate with respect to silicon measurements. On the other hand, physical design tools are traditionally guided by geometric constraints. In interconnect-dominated designs, both parasitic-aware circuit optimization and performance-driven physical design are crucial for rapid design closure. This thesis addresses both issues by integrating schematic optimization and the physical design process. Through the use of virtual interconnect parasitic models and light-weight parasitic models, the simulation-based circuit optimizers and placement tools can exchange design and performance information while operating at their full capacities. The interconnect models also provide provisional routing configurations. A novel compaction process for analog layout further refines the block and interconnect positions with respect to DSM effects.