The Design And Optimiation Of 40nm Technology High-Speed DAC Circuit Units

21st century is the age of information,digital signal processing system and the signal conversion system play an important role in the interactions between h?m an and the digital society.Digital to Analog Converter(DAC: Digital-to-Analog Converter)is the core circuit to realize signal conversion and interaction.In recent years,along with the rising of the SOC working frequency,the shrink of the integrated circuit manufacturing feature sizes,the design and production of DAC circuit facing a series of challenges.On the other hand,the 40 nm Integrated Circuit manufacturing process has a mass production,the related research on device and manufacture are already mature.Aiming at this phenomenon,we regard the Digital-to-Analog Converter as research object in this paper,based on SMIC 40 nm IC manufacturing process,design a high-speed current steering Digital-to-Analog Converter with 6bit input digits and 16.5GHz clock input signal frequency.Proposed an optimized method for the core circuit unit in D/A converter,finally complete the post-layout simulation,tape-out and test work.Specific results from research are follows:First of all,the DAC circuit working mechanism is designed.Based on the comparison of each DAC structures performance advantages and dis advantages and design specifications,decided to use “4+2” subsection current steering structure as the DAC structure.In this kind of structure,high four digital bits use thermometer code and two low digital bit use binary code.Secondly,this paper determines the system structure of DAC circuit,the key circuit units include switch and current source array circuit,MUX array circuit and clock divider circuit.Besides,this paper researches the non-ideal effects and the parasitic parameter,which may interference the circuit performance.Thirdly,the design and performance optimization projects of switch and current source array circuit,MUX array circuit and clock divider circuit are given.The switch and current source array circuit is made up of NMOS devices,use cascade transistor to reduce the difficulty of match and hold the output impedance.The MUX array circuit use one dimensional configuration and five pipeline stage structure,which make input signal accelerated from 1GS/s to 33GS/s.In the static timing analysis process,changed the structure of clock driving circuit from tree distribution to chain distribution,which enhanced the high-frequency clock signal anti-jamming capability.The clock divider circuit is made up of inverter,buffer and D flip-flop,The input clock signal is divided into five different output signals with different frequencies.Use single side turn to differential circuit to keep the stability of 16 GHz high-frequency signal.On this basis,the layout design and related simulation are carried out.The results show that the circuit can work properly and the parameters meet the requirements of the indicators.Fourthly,the steering DAC top layout floorplan is given and the layout of steering DAC circuit is designed.The circuit function and related performance parameters were verified by simulation.The results show the circuit performance meet the design requirements.After tape-out,chip package,PCB design and chip testing are conducted.Through tape out and testing,the number of significant digits type current steering DAC circuit for 6 bit,about 16 GHz monitoring to the stability of the clock frequency,the maxim?m clock frequency of 16.65 GHz;Circuit is one of the biggest data sampling rate is 32 Gs/s,circuit of two important parameters of the INL and DNL is approximately 0.1 LSB and 0.3LSB,basic indicators reached the design requirements.