Research And Implementation Of Real-time Image Edge Detection System Based On FPGA

When performing image processing,the edges of the image are usually more critical,because the most important targets that need to be extracted in the image are usually included in the edge,and the most representative points in the edge information can be found after converting the image into pixels.Regardless of the compression of the image or the feature extraction of the image,the edge of the target image must be detected before processing the next operation.Therefore,the application of edge detection technology is very extensive and almost requires image processing involved.It is a very common technique for all image areas to detect their edges,so edge detection is also practical.In this paper,the image data is collected by using OV5640 camera.The collected image data is stored in SDRAM DDR3 memory chip,and the four asynchronous FIFOs are used as the buffer of data ping-pong operation,and then the Sobel algorithm module is implemented on the hardware development platform FPGA.Convolution operation on the image data buffered in SDRAM DDR3 realizes the effect of edge detection processing.Finally,the processed image data is displayed on the HDMI liquid crystal display through the HDMI display module.The main modules of this system include OV5640,FPGA.The SDRAM DDR3 and HDMI modules together form an image edge detection system.The original intention of the design at the beginning of this paper is to solve the problem of fast processing edge detection image algorithm.However,at present,whether the image is processed by the host computer or the edge processing of the image by multiple CPUs,the speed of the processing algorithm is not too fast.In addition,it is more troublesome to deal with floating-point numbers in hardware.Therefore,in order to better meet the requirements of real-time performance,this paper performs heterogeneous design on the algorithm,accelerates the edge detection algorithm,and improves the code with the underlying C/C++ code.The Sobel algorithm then optimizes the algorithm.In this paper no area or resource optimization is performed,mainly in terms of speed,and the speed is optimized by means of a pipeline.It can be seen from the comparison of the report that the Latency and Interval are reduced before the optimization.Finally,the C/C++ and RTL code co-simulate,the generated new IP can be used in the Vivado project,that is,encapsulated into an IP.After building a complete project,the display is performed on the HDMI liquid crystal display,and finally the design effect is achieved.