Research On Low Power Consumption Physical Design Based On 40nm Process MCU Chip

With the rapid development of the integrated circuit(IC),electronic products are becoming more and more popular.Especially with the development of semiconductor technology,the increasing frequency and integration of chips,power has become a key factor that IC designers must consider.Researching efficient low-power methods has become more and more important.Based on the 40nm process,this paper implements a low-power physical design of an MCU chip.The chip scale is about 6 million gates and the clock frequency is 180MHz.This article is based on Synopsys' latest layout tool IC Compiler II for related low-power physics design.The article first introduces the development history of IC and the research status of low-power,introduces the power theory of CMOS.On this basis,the low power idea of 40nm process is proposed.It also introduces several low-power methods in physical design.Finally,the implementation of the low-power method of the MCU chip is elaborated,and the significant of the low-power method proposed in this paper is proved by the power comparison analysis.In floorplan stage,different placement and power pin connections are adopted according to the structure of different low-power cells.In particular,this article does not take the traditional power rail supply method in order to make level shifter fully powered,but the power pin is prerouted connected to power stripes.Therefore,the voltage swing of the signal reaching the area is matched with the voltage of the area.In the clock tree synthesis(CTS)phase,in order to reduce the clock network power more effectively,this paper proposes a new method:place clock tree cells by manual.The general CTS method tends to sacrifice power in order to ensure timing.But this method aims at clock skew and insertion delay,ensuring fast convergence of timin g while reducing power.First analyze the clock structure,divide the clock network into three segments and balance them separately.Then manually place the clock tree cells to reduce power more effectively.The results show that this method can reduce the clock network power by 27.9%.Not only that,but this paper also proposes a new method of clock-gating technology.Traditional clock-gating method sometimes insert too many integrated clock gating(ICG)cells,causing them to increase power themselves more than shutdown power.The method places the ICG as close as possible to the root of the clock tree,which reduces the number of ICG and turns off more clock cells,thereby further reducing power consumption.The results show that this method can further reduce the clock network power by 10.1%based on the traditional clock-gating.Both methods have significant effects,greatly improving the performance of the chip.