The Desgin And Implementation Of 2.5Gbps Optical Receiver Preamplifier

Optical fiber communication is playing an increasingly important role in the information age.It has unique features such as low signal attenuation,large transmission distance,large signal bandwidth capacity,strong anti-interference ability,safety and reliability,and lower cost.It is precisely because of the incomparable characteristics of optical fiber communication that the backbone networks of communication all over the world are increasingly using optical fiber communication.The optical receiver preamplifier is one of the most core components in the optical receiver,and its parameters directly affect the performance of the optical receiver.At present,the optical receiver preamplifier is usually packaged with the photodetector and together determines the receiving sensitivity of the optical receiver front end.Since the photodetector output current signal is often very weak,it imposes strict requirements on the noise performance,channel gain,and signal bandwidth of the preamplifier.To achieve the balance of various indicators,it is necessary to improve the structure and parameters of the preamplifier.Because of the huge demand,cost is also considered.Because of its mature system and cost advantages,CMOS technology has gradually become the mainstream technology of optical receiver preamplifiers.How to overcome its various parasitic parameters and develop product performance to the extreme is called the current research hotspot.This article uses the 0.18?m CMOS technology platform,from the schematic to the layout,to design a 2.5Gbps code rate optical receiver preamplifier.Starting from the optical receiver system architecture,the technical specifications of the preamplifier are described,the important role of eye diagrams in digital systems and important parameters are introduced,and the bridge between chip-level parameters and system parameters is built.This article comprehensively designs the unit components required by the preamplifier,from transimpedance amplifiers,signal channels,to signal strength indicator units,cathode bias circuits,power management circuits,etc.,to achieve complete functions,design practical amplifier chips,and The performance of each module is simulated to ensure that each unit achieves the expected performance.In the study of the core transimpedance gain stage of the preamplifier,this paper compares the performance of three transimpedance amplifier structures in detail,and selects a resistance-negative feedback transimpedance structure with balanced performance.In this paper,cadence is used to extract the parasitic simulation of the whole chip.Each simulation parameter meets the design specifications.The channel gain reaches 7.7K?,the-3dB bandwidth reaches 2.1GHz,and the input reference noise current is 320 nA.The reliability of the chip is carefully designed,and the ESD scheme is designed.The chip was taped out,and the die and photodetector PD were packaged in TO-CAN for testing.An optical receiver front-end test platform has been established to test the receiving sensitivity of the chip under typical application conditions.The ordinary PIN-TIA can reach-26 dBm,the APD-TIA can reach-33 dBm,the actual chip power consumption is 19 mA,and the chip size is 1208?m ×1080?m.