High Speed Front-End Amplifiers Design Of Optical Receiver For Optical Interconnect

With the frequency improvement of integrated circuits, it is very difficult for the traditional electrical interconnection to transmit 10Gbps or above signal on PCB, because of some shortcomings exist, such as attenuation, cross-talk and impedance matching, which have become the bottle-necks during the improvement of the system performance. Compared with the electrical interconnection, because of its advantages such as high bandwidth,low attenuation,no cross-talk,no impedance matching and low Electro Magnetic Interference(EMI), optical interconnection is a good choice to replace of the traditional electrical interconnect.In the building blocks of an optical interconnect system, the preamplifier and the main amplifier are the critical parts. The task of this project is to design a preamplifier and a main amplifier for 2.5Gbps optical receiver using SMIC 0.18μm CMOS technology and integrate the front-end amplifier monolithically, meanwhile, try to decrease cost, size and power dissipation of the chip.The performance of a preamplifier has great effect on the performance of an optical receiver. The Regulated Cascode(RGC) configuration is exploited as the input stage of the transimpedance preamplifier, which isolates the large input parasitic capacitance including photodiode capacitance from the bandwidth determination. On the basis of theory analysis and design optimization, the circuit achieves high performance of gain, bandwidth and power dissipation.An automatic Gain Control (AGC) amplifier or a limiting amplifier is generally used to realize the main amplifier. The latter one was chosen to realize the main amplifier in our design. A differential common source amplifier is used as the basic amplification cell. The direct-coupled technology is employed between different amplification cells to reduce the power dissipation.In this paper, we describe the whole procedure from the circuit design to layout design. Cadence Virtuoso simulations demonstrate -3dB bandwidth of 1.92GHz for 0.62pF photodiode capacitance from a single 1.8V supply. And when the input current amplitude is 30μApp, the output voltage of 50Ωload is achieved to be more than 500mV. The front-end circuit has a good eye diagram at 2.5Gbps pseudo random bit sequence. The simulation results also demonstrate the front-end circuit with DC consumption of 109mW.