On-chip Network Routing Optimization For Multicore Cache Coherence

With the continuous development of semiconductor process technology,system-on-chip faces a series of problems such as leakage power consumption,integrated circuit design has gradually shifted from high-performance single-core CPU design to high-performance multi-core communication network design,due to the increasing number of cores integrated in multi-core chips In many cases,the on-chip interconnect structure gradually evolves from bus point-to-point interconnection to on-chip network disordered interconnection.Compared with the traditional bus interconnection structure,the on-chip network has greater development potential for parallel computing,and has gradually become a research hotspot of multi-core and even many-core systems.As a huge communication system,the on-chip network can be studied from the aspects of topology,routing algorithm,flow control mechanism,and router microstructure.For different application scenarios,the on-chip network can achieve different customized optimizations and improve network performance.The change of communication interconnection structure makes the traditional snooping coherence protocol applicable to the bus structure no longer effective.New cache coherence protocols such as directory protocol and token protocol place new requirements on the on-chip network.Based on the characteristics of multicast traffic exhibited by the multi-core cache coherence protocol on the on-chip network,this article starts from two perspectives: implementing a routing algorithm for adaptive and smaller multicast trees and designing a hardware multicast replication router that supports the multicast algorithm,and optimizes the on-chip network.The whole area adaptive recursive partitioned multicast routing algorithm designed in this paper,based on the premise of the shortest path routing,realizes the link reuse of multicast packets as much as possible,effectively improves the network load capacity,and supports the whole area of adaptive routing at the same time.It also reduces the average packet transmission delay.Through simulation experiments,under the excitation range of 3.88% to 64% of the proportion of multicast packets,the average throughput can be improved by 23.61% relative to the benchmark DPM routing algorithm,even compared to the partially adaptive optimized DPM algorithm.Increase by 5.30%.The adaptive multicast replication router designed in this paper can perform synchronous parallel multicast packet replication and serial multicast packet replication adaptively according to the network congestion without consuming additional hardware area.Compared with the traditional unicast router and the single-read pointer serial replication router can significantly reduce the data packet transmission delay and improve the network throughput rate.Through simulation experiments,under the excitation range of 3.88% to 64% of the proportion of multicast packets,the saturation throughput rate can be increased by an average of 41.14% relative to unicast routers,and the average increase can be 6.06% relative to serial multicast replication routers.The hardware implementation of this article uses verilog language,and the simulation platform is built with systemverilog.Under the random excitation of multiple multicast packet loads,the results show that the adaptive multicast replication router designed in this paper and the whole area adaptive recursive partitioned multicast routing algorithm can effectively support multi-core consistency to cause multicast traffic and reduce data packets.Transmission delay,optimized data transmission efficiency,improve network throughput,and improve on-chip network performance.