The Research And Implementation Of Multi-rail Multiplication Algorithm Based On NCL

With the continuous enhancement of microelectronics technology,the scale of integrated circuit is increasing day by day.Under the condition that the area of chip is gradually shrinking,the processing of a large number of data is more frequent,so there is a higher requirement for the structure and operation efficiency of digital processor.In the past few decades,synchronous circuit design has been the focus of digital circuits.However,with the increasing of clock frequency and the decreasing of chip feature size,there are more and more problems,such as clock skew,excessive power consumption and so on.The asynchronous circuit has the natural advantages of low power consumption,low noise and less electromagnetic interference,so the design idea of the asynchronous circuit without clock becomes the focus of people's attention again.This paper has studied the operation in asynchronous circuit system and completed,based on Null Convention Logic(NCL)method,the design and implementation of a multi-rail 8-bit multiplication algorithm.First,a deep understanding of working principles such as Booth algorithm and compression algorithm has been explored to realize NCL optimized Booth coding algorithm and make reasonable use of half-adder and full-adder to construct the Wallace tree structure.The quad-rail addition algorithm and circuit are designed according to the characteristics of the quad-rail circuit,so as to improve the overall performance of the multiplier.Secondly,three dual-rail 8-bit multipliers and a quad-rail 8-bit multiplier are implemented on the Vivado platform with methods mentioned above.Finally,based on the analysis and comparison of the performance of different multipliers,the result shows that the dual-rail multiplier based on the multiplication algorithm in the paper is superior to the quad-rail multiplier in terms of both area and calculation speed,and the dual-rail 8-bit multiplier applying NCL optimized Booth algorithm andoptimized Wallace tree structure has advantages in speed(up to 23.5ns)and area.