Research And Design Of Multiplier In High Speed DSP Chip

There are so many digital signal processing problems now.Information science has penetrated into all modern natural sciences and social sciences fileds.Since the 1980 s,with the rapid development of integrated circuit technology,using hardware to process digital signal has came ture,thus accelerating the development of the digital signal processing.Many of the high-speed,dedicated digital signal processing chips,the most important of which is the dedicated digital signal processing chip(DSP chip),have been developed what release the advantages of digital signal processing technology.Today,the mainstream digital signal processing solutions are: dedicated DSP chip and ASIC;programmable DSP chip;FPGA chip.Among them,DSP chip play an increasingly important role in various applications,due to its high performance,low power consumption and cost-effective.With the gradual development of modern information industry,many applications gradually develop from using software system to deal with digital signals to using hardware system to deal with digital signal,and DSP chip is the core technology to achieve that.Therefo,the DSP chip is important for the development of digital signal processing technology.The performance of the multiplier and adder in the hardware circuit determines the performance of the DSP chip,which also determines the ability of the signal processing system to process the signal.In this paper,through studing and summarizing the existing multiplier,I multiplier optimization algorithms,and use the base 4 Booth improved code generation partial products method and Wallace Tree compression partial product design two kinds of high speed multiplier of 16 bit * 16 bit.These multiplier have been proved that work well and achieve the desigen goals.Design based 4 Booth algorithm improved code multipliers,optimizeing the partial product generation,reducing the number of partial products,so as to enhance the performance of the entire circuit.Design a based Wallace Tree algorithm multiplier,optimizing the partial product generation method on the basis of the Booth algorithm,using bitwise coding,and using a five-election circuit to facilitate the circuit design.Use process of 5-3 compression in Wallace Tree compression,reducing the number of compression layers to improve the compression efficiency.Use the square root of the sum selection adder to calculate the last two 32-bit data,reducing latency.Design a inverter chain for the multiplier,enhance the capacity of the circuit for driving a load.Wallace Tree multiplier has a delay of 4.752 ns and an area of 3878.44 square microns,which are better than the original Pozz code multiplier performance and the design in the comparison literature.