Design Of Real-time Image Edge Detection System Based On FPGA

With the developing of industrial technology,image processing is more and more important in society.As the basic feature of image,image edge has a lot of key information and the quality of edge detection plays an important role in subsequent image processing.However,with the development of image technology,image transmission data is getting larger and larger,and the software-based digital image processing is sometimes unable to meet the real-time requirements of image technology.Because of the high speed parallelism and pipeline structure of FPGA,it is very suitable for fast image processing.In view of the characteristics of long time and low real-time of traditional image processing,this paper constructs a real-time image edge detection technology based on FPGA,which mainly includes four modules:acquisition,storage,processing and display.In the image acquisition module,the configuration of OV5640 image acquisition mode is completed through the IIC interface protocol.In the storage module through the SDRAM to complete the image cache Settings.In the display module,the image is displayed on the display screen through the VGA interface.Due to the large computation and time consuming of the median filtering algorithm currently used,it cannot be realized quickly on the hardware.In this paper,based on the median filtering principle,a fast median filtering algorithm is implemented by using the parallelism of comparison function and FPGA to reduce the time consumption of median filtering.In the image edge detection module,the Sobel edge detection algorithm was improved,two templates were added at 45~o and 135~o,and the four-template algorithm was combined with Roberts edge enhancement to perform color double-edge detection on the image.With the help of the threshold value of Canny operator,the dynamic threshold value is set by the pixels in the template to realize the automatic threshold processing of the whole edge detection system.Realizing the compilation of the whole program by Verilog HDL language in Quartus II software.After the system design is completed,Modlesim software is used to simulate the module in image processing to verify the module design timing sequence of the system.Finally,the compiled file is downloaded to the FPGA to complete the experimental test.By comparing with the edge detection graph obtained by Matlab and the traditional Sobel graph,it can be obtained that the system can complete the real-time image edge detection.The experiment proves that the improved Sobel algorithm can enhance the edge detection effect and obtain better edge effect.