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Threshold Voltage Model Of Ge MOS Devices And Study Of ZrLaON Gate Dielectric

Posted on:2020-12-02Degree:MasterType:Thesis
Country:ChinaCandidate:B Z LiangFull Text:PDF
GTID:2428330590450370Subject:Software engineering
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With the development of integrated circuits,MOS devices continue to scale down,silicon-based MOS devices have gradually approached their physical limits.While having higher electron and hole mobility than silicon,germanium materials have become the bottom materials which have great application prospect,and their Ge MOS devices have received extensive attention from researchers at home and abroad.One of the key problems hindering the application of Ge-based MOSFET is the interface quality between Ge substrate and high-k-gate dielectric.In this paper,the Ge MOS devices are studied theoretically and experimentally.In the theoretical aspect,the threshold voltage model of stacked high-k-gate dielectrics fully-depleted GeOI pMOSFET in view of fringing capacitance is established.In the experimental aspect,improving the effects of Zr-based binary oxynitride high-k-gate dielectrics and NH3 plasma treatment on the devices'interfacial and electrical properties is investigated.In the aspect of theory,by solving the two-dimensional Poisson equation and considering the fringing capacitance of gate electrodes to the source and drain region,the threshold voltage model of stacked high-k-gate dielectric GeOI pMOSFET considering about short channel effect?SCE?and fringing field effect is obtained.And the calculation results of the model quite coincide with the experimental data,The simulation results show that the fringing field effect can be suppressed by reducing drain-source voltage,reducing dielectric constant of the high-k-gate dielectric layer when the equivalent oxide thickness remains unchanged,and reducing channel thickness.And the simulation results also show that adding interface passivation layer,reducing channel thickness and increasing channel doping concentration can suppress SCE effect of small size devices.In the aspect of experiment,?1?Ge MOS capacitors with ZrON,ZrTaON,ZrAlON and ZrLaON as high-k-gate dielectric was fabricated,and the effects of different elements doped in ZrON on interfacial and electrical properties of Ge MOS were investigated.The experimental results show that the doping of La,Al and Ta can reduce the formation of GeOx at the Ge interface and improve the quality of the interface.And the best interfacial quality and electrical properties were obtained by doping La:low interfacial-state density:Dit(2.08×10122 eV-1cm-2),low frequency dispersion and small gate leakage current density Jg(2.85×10-44 A/cm2@Vg=Vfb+1 V).?2?On the basis of?1?,ZrLaON/Ge MOS capacitors with different La content were fabricated,further analyze the effect of La content on ZrLaON/Ge interface,and the improvement of NH3 plasma treatment on the interface characteristics between high-k-gate dielectric and Ge was investigated.The experimental results show that proper La doped can reduce the roughness of ZrLaON gate dielectric film and effectively improve the interface quality and electrical characteristics of the device;Excessive La doped will increase the roughness of gate dielectric film and deteriorate the device performance.On the other hand,surface treatment by NH3 plasma can improve the relative dielectric constant of the gate dielectric,reduce the equivalent oxide electric density,interfacial-state density and gate leakage current,and further reduce interface defects and improve the interface quality and electrical characteristics of Ge MOS device.
Keywords/Search Tags:Ge MOS devices, Threshold voltage, High-k gate dielectric, Interface-state density, Plasma treatment
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