Threshold Voltage Model And Interfacial Characteristics Of GaAs MOS Devices With High-k Gate Dielectric

In recent years, Si-based integrated circuit has been gradually close to its physical limits, and GaAs, one of III-V compound semiconductor materials, has attracted great research interest for application in the high-k gate dielectric MOSFET devices due to its large band gap, high electron mobility and low power consumption etc. However, the formation of the native oxides on the surface of GaAs can lead to an interface with poor quality between high-k gate dielectric and GaAs semiconductor. Therefore, in this paper, the study mainly focus on the properties of the high-k/GaAs gate dielectric interface. As for the theoretical study, a threshold-voltage model for stacked high-k gate dielectric GaAs MOSFET is established, and the impacts of structural and physical parameters on the threshold-voltage are investigated.An accurate threshold-voltage model for the stacked high-k gate dielectric GaAs MOSFET is established by solving two-dimensional Poisson's equation in channel and considering short-channel, DIBL and quantum effects. Using the model, the temperature characteristics of the threshold voltage have been discussed, and the results show that the influence of the temperature on the threshold voltage is overestimated if the quantum effect is ignored. Also, the influences of introducing a low-k interlayer on threshold voltage has been studied, showing that using a low-k interlayer can improve interfacial properties, suppress the fringing-field and DIBL effects, and thus improve the threshold behavior and temperature stability of GaAs MOSFET, however, a reasonable thickness and k value of the stacked gate dielectric are needed to obtain a good trade-off between threshold voltage and gate leakage current.Researches on experiments include two parts.(1) GaAs MOS capacitors with N2- or NH3-plasma surface pretreatment and LaON interfacial passivation layer(IPL) are fabricated, and their interfacial and electrical properties are investigated and compared with their counterpart with neither surface treatment nor LaON IPL. The experimental results show that the sample with LaON IPL and NH3-plasma pretreatment exhibits good interface quality and excellent electrical properties.(2) The HfTiON/LaON/La GaAs MOS devices are fabricated, and the impact of metal La on the device properties and the influence of different annealing temperature processing on the metal La IPL are studied. The experiment results indicate that HfTiON/LaON/La GaAs MOS device possesses the most excellent electrical properties by using LaON/La as IPL and annealing at 600 ? environment.