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Research On Many-Core Cache Coherency Based On Network On Chip Architecture

Posted on:2019-06-14Degree:MasterType:Thesis
Country:ChinaCandidate:A M ZhangFull Text:PDF
GTID:2428330548986773Subject:Electromagnetic field and microwave technology
Abstract/Summary:PDF Full Text Request
The research of on-chip multi-core system has moved from academic to industry.Such systems with high-performance and low-cost are in urgent need for practical applications.With the increasing of processors,the cache coherence problem becomes more and more prominent.Researchers have laid a solid foundation on data coherence architectures based on bus or network-on-chip(NoC),respectively,but data consistency based on the two-layer architecture still needs a lot effort to explore.In this work,I focus on designing a two-layer hybrid coherence architecture based on NoC.The main contribution is as follows:1?Designing a double-layer hybrid data-coherence architecture based on NoC.For the cache coherence problem of multi-core processors,a two-layer hybrid coherent architecture based on network on chip is designed and implemented.According to the different architectures of multi-cores,different data consistency protocols are used to achieve higher data throughput.For multi-core caches based on bus architectures,bus monitoring protocols are used to improve efficiency.For multi-core caches based on NoC,a directory protocol is usually applied,which is not affected by the network size and is easy to extend.Experimental results show that the use of dual-architecture mixed consistency based on multi-core system,can effectively reduce the consistency of execution time by 48.5%.2?Proposing a global and local data consistency protocolBased on the existing two-layer architecture applying the mixed consistency,this paper proposes a method of adding block transmission function to reduce the average waiting time of the core and increase the data processing speed.According to the characteristics of data exchange among cores,the idea of combining global data and local data is proposed to reduce the directory occupancy ratio and decrease costs.Through experimental analysis,block transmission can raise the average processing speed of the core.When the number of nodes is 4,the combined global and local protocol can lower the directory occupation ratio by 75%.
Keywords/Search Tags:Network on Chip, Cores, Consistency, Two-layer architecture
PDF Full Text Request
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