A Study Of Topology For Three-dimensional Network-on-Chip Of Thousand Cores

In recent years, multi-core chip plays an increasingly important role in big data processing. With the rapid increasing of transisitor technology, chip with hundreds or even thousands of cores has been proposed. Network-on-chip (NoC) has emerged as an alternative way to solve the problem faced by shared bus structure. Three dimensional integrated circuit (3D IC) that stacks multiple silicon dies is emerging as a promising solution to overcome the limitations in chip integration. By combining the advantages of 3D IC and NoC, three dimensional Network-on-Chip (3D NoC) is considered to be the most promising paradigm for the design of thousand cores chip. Unfortunately, due to the immature fabrication process of through silicon via (TSV) connections, the yield of 3D NoC decreases sharply with the number of TSVs increasing. The large number of TSVs cannot be neglected any more due to the low yield and high overhead of TSVs. Therefore, it is necessary to design a topology for thousand cores NoC which can reduce the nubmer of TSV applied and improve the performance of chip at the same time.In this thesis, we firstly introduce the research background and current development of the 3D NoC, sum up several inter-layer connection methods in 3D NoC and sketch the manufacturing process and packaging technology of TSV, which is the most promising 3D technology. Besides, the inter-layer communication method based on TSV is studied. Secondly, we analyze several common 2D topologies and 3D topologies extended from the 2D ones. Thirdly, given the fact that the manufacturing cost of 3D NoC grows exponentially with the increase of the adopted TSVs owning to immature technology, a hybrid vertical interconnection scheme is proposed to reduce the number of TSVs by sharing vertical links through vertical routers. The simulation results show that sharing scheme can provide acceptable performance while reducing the number of TSVs between layers by 50%, and can significantly improve the yield of the chip and reduce the chip area and power consumption. Based on the proposed hybrid vertical interconnection links sharing schemes, a novel 3D topology for thousand cores NoC called Hcluster and a new corresponding deadlock free dimension order routing algorithm are proposed. Hcluster, together with the proposed routing algorithm, can realize minimum hop count communication in 3D NoC. A simulation platform is developed to evaluate the performance of Hcluster in latency reduction, throughput enhancement and chip yield increase by OPNET. The simulation results show that Hcluster can improve the yield of many-cores chip and has a much better performance. Moreover, Hcluster is of good performance in extension, hence it is flexible to enlarge the scale of network to hundreds even thousands cores.