VLSI Low Power Design & Research

As the semiconductor manufacturing process technology into the deep sub-micron or even nanometer, power consumption is becoming increasingly prominent. The proposing energy saving and environmentally friendly national policy and low carbon concept deeply rooting among peoples, the VLSI low power design is becoming increasingly important. This paper uses different design methods/flows to complete two design, and analyzes the low power techniques, results of design and impact by introducing low-power architecture.First of all, the ring delay chain (RDL) module in time-digital converter (TDC) system implementation process illustrates the custom process for low-power design and the solutions for following problems.Second, this paper illustrates the hardware description language based and unified power format (UPF) based very large scale integrated circuits (VLSI) low-power design process, and its implementation processes based on EDA tools, using the embedded processor OR1200LP design. With UPF, low-power intents of the designer are described, such as power domains of OR1200LP, power switches, isolation cells, level shifters, Retention Register, power state table (PST). Power-gateing and multi-voltage/ multi-supply low power strategies be brought to circuit, to establish OR1200LP low-power architecture and complete the design layout by using EDA physical synthesis and P&R tools.Finally, the clock gating and static multi-voltage (SMV), dynamic voltage frequency scaling (DVFS), power gating (Power Gating), multi-threshold (Multi-VT), and low-power design techniques related issues are discussed, and design effect of reducing the power consumption is analyzed.The innovations of this paper include:·A new sampling structure is proposed, ensuring that the location of the turn signal is accurately determine when circuits stay in metastablility,effectively reducing design short-circuit power consumption and increasing the design accuracy. ·With exchanging gate pin, a lower energy consumption RDL structure is obtained.·A control strategy of software algorithm controls+hardware timing controls for dynamic voltage scaling with power gating. Adjusting different dynamic voltage scaling (DVS) with power gating algorithm by modifying software improves the design of flexibility. Control hardware implements the power on/off scheduling of modules. And thus reduce the power consumption value.·Get a low IR-drop and electronmigration power network distribution by determining the location and quantity, and power planning; through the use of daisy chain structure to achieve the connection of PowerSwitch control signal, the rush current is decreased;The final results of designs show that the improvement of the power consumption is obvious.