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Implementation And Optimization Of Context Management Structure Of Reconfigurable System For Block Cipher Algorithm

Posted on:2016-07-05Degree:MasterType:Thesis
Country:ChinaCandidate:J B HuFull Text:PDF
GTID:2308330503977125Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Reconfigurable system is suitable for data-intensive applications due to the combination of flexibility and efficiency. Cipher algorithms need to deal with large amount of data. The combination of cipher algorithms and reconfigurable technology can meet the requirements of performance and security. As the complexity and algorithm performance demand increasing, the computing resources of reconfigurable system also increases. The amount of context in reconfigurable system increases leads to more configuration time, which affects the performance of the system. Therefore, it plays a very important role to establish a set of effective configuration management strategy to improve the performance of reconfigurable system.A set of management solution suitable for the block cipher algorithms is put forward. First, the content of block cipher algorithms is analyzed to summarize its configuration characteristics:context reusability of round function, context reusability of operators, and locality of configuration-switching. Then according to the configuration characteristics, the hierarchical context organization scheme based operators is designed to compress the context because of excessive context, and the partial reconfiguration and pipeline scheduling scheme is designed to reduce the configuration time because of too long configuration time. The circuit implementation scheme is also given, and the line of computing resources, interconnections and control units are chosen as the granularity of reconfiguration. At last,3 block cipher algorithms are mapped to generate context on the basis of the proposed configuration management scheme.The circuit was realized finally under TSMC 45 nm CMOS technology, with the area of 2.12mm and frequency of 500 MHz. The area efficiency of DES, AES and SM4 achieved 2.33Gbps/mm2, 30.19Gbps/mm2,1.08Gbps/mm2, which was superior to the design target. Concretely, the proposed scheme effectively compresses the amount of context to about 79.5% of the same type scheme. The ratio between configuration time and total time of DES and SM4 was reduced to 0.55% and 0.55%, and hidden time accounted for 88.89% and 88.89%; The area efficiency of 3 algorithms was improved over 49% than the existing CGRA architecture.
Keywords/Search Tags:reconfigurable system, block cipher algorithms, configuration management, hierarchical context, partial reconfiguration
PDF Full Text Request
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