Super-threshold Standard Reed-Muller Logic Cell Library And Dual Logic Mapping

Many studies have shown that Reed-Muller logic circuits have better performance in area and power consumption than the traditional Boolean logic circuits.With the high-speed and low-power design purposes,Cell-Based semi-custom design become main method of modern integrated circuit.However,the existing Cell-Based libraries are based on the traditional Boolean logic CMOS circuits,which is not suitable for RM logic and FinFET devices circuits study.We need to re-design the FinFET devices cell library based on RM logic.In this paper,we re-designed the RM basic logic circuits and three-input RM composite circuits.We also designed the super-threshold RM logical cell library,which can be identified by EDA tool and verified by dual logical mapping tools.This paper includes the following several aspects:1.Super-threshold standard Reed-Muller logic circuits design.Re-design the basic circuit of RM logic and the three-input RM composite gate circuit.Optimize the re-designed circuit by super-threshold technology.2.Super-threshold standard Reed-Muller logic cell library design.Simulate the new ReedMuller logic structure with Cadence and Synopsys' s EDA software.Design the layout of standard cell library.Calculate the independent gate FinFET's parasitic parameters.Extract the physical library and timing library.3.Dual logic mapping.Make sure the RM logic cell library can be recognized by DC tools.Use 4-bit multiplier map dual logic.Analyze the mapping result.We have analyzed the performance of the RM circuits and the three-input RM composite circuits with the HSPICE simulation software.The power consumption of the RM logic circuit is 33.41%-49.64% lower than the traditional structure.The power consumption delay product is reduced by 12.14%-54.31%.The library is verified through a 4-bit multiplier.The results showed that the library can be used with EDA tool and the synthesized circuits are optimized with area and power consumption.Most of the existing FinFET circuits are simulation without parasitic parameters.The parasitic parameters and layout design of independent gate FinFET devices are lack of open standard cell library which can be used in EDA tools.In this paper,the cell layout is based on the FinFET circuit and the parasitic parameters are analyzed by BSIM model.The results of the simulation are more accurate.This paper filled the missing field of simulation studies in FinFET circuit design and RM dual mapping logic.Academics can use the hardware description language to simulate the circuits with parasitic parameters and automatically generate layouts.It provides an important reference for the simulation research of FinFET circuit and RM logic.