The Study And Implementation Of PA-resistant Logic Styles

The traditional cryptanalysis is aimed at the security of the cryptographic algorithm itself. However, a new technique which is called side-channel attack is introduced recently. While the secret key in the cryptographic module is processed, some side-channel information such as the computation time, the power consumption and the electromagnetic emanation of a cryptographic module leaks information about the secret key. The side-channel attacks will find the secret keys by analyzing the side-channel information. Power-analysis (PA) attack is one of the most powerful side-channel attack techniques against cryptographic modules. In such an attack, the power consumption of a cryptographic module is analyzed to reveal the secret key that is used inside the module.Today, the static complementary CMOS logic style is widely used to build integrated circuits. The power consumed by CMOS circuits depends on the data being processed by the circuits. The correlation between power consumption and the data being processed is the fundamental reason why side-channel information is leaked through the power consumption. The leaking information has no influence on non-security applications but it poses a serious threat on the implementations of cryptographic algorithms. Therefore, when such cryptographic modules are designed, the designers have to take various measures to counteract these attacks. Many countermeasures to handle this problem have been already published currently. Some of the approaches try to solve the problem on the algorithmic level, and others try to handle it on the hardware level. Some of the hardware approaches are based on a dedicated architecture of the basic logic gates. In this approach, PA-resistant logic style, instead of the static complementary CMOS logic style, is used to implement cryptographic modules. In this thesis, the PA-resistant logic styles are studied and analyzed.SABL and DDCVSL are two typical PA-resistant Logic Styles. In this diploma thesis, we design and implement two different PA-resistant standard cell libraries using a full-custom design flow under the process technology SMIC 0.18μm. Then, PA-resistant cryptographic modules are designed using the PA-resistant standard cell libraries. The PA-resistant standard cell library can not be integrated in a typical semi-custom design flow directly, As a result, an adapted semi-custom design flow is proposed.Generally speaking, the SABL logic style is usually regarded to be better than the DDCVSL logic style. In this thesis, we analyze the two different logic styles. The main criterion is the side-channel information leaking through the power consumption. Beside this, we consider the overall power consumption, the circuit complexity and some other parameters relevant to practical implementations. All parameters of the logic styles are determined based on Spice-level simulations. The comparative result demonstrates that the DDCVSL logic style becomes more suitable to implement cryptographic module than the SABL logic style, with development of the process technology.In one word, the main objectives of this diploma thesis are to show how to implement and to characterize the PA-resistant standard cells, and how to implement a PA-resistant cryptographic module using an adapted semi-custom design flow. Moreover, the resistance of two different logic styles (DDCVSL and SABL) against power analysis attacks is analyzed, and the influence of process technology on the PA- resistant logic is concluded.