Study And Design Of CMOS Power Amplifiers For Wirless Communications

With the continuous prosperity and development of the wireless communication market,wireless devices with low cost,high power efficient,reliable performance and small form-factor are demanded by today's consumers.CMOS technology has its unique advantages in cost and integration,and by using it,most of the modules in transceiver design can be achieved without sacrificing performance.However,power amplifier,often as the most power-hungry and area-occupation module in modern transceiver,is still among those few remaining modules that haven't been successfully integrated yet.Based on different wireless standards,the thesis mainly conducts the research on the phase&litude control,reliability,integration and power back-off efficiency of CMOS power amplifier.For the self-jammer problem in UHF RFID application,this thesis proposed a full-integrated phase&litude digitally-controlled power amplifier which mainly consists of an active phase shifter,a buffer and a gain-controllable power amplifier.Principle and structure of each module are discussed in this thesis.To reduce the AM-PM distortion of power amplifier,a capacitance-compensation technique is adopted in the gain-controllable power amplifier.The power amplifier is implemented in 130 nm CMOS process,simulation results illustrate that the digitally-controlled power amplifier achieves less than ldBm power variation and 0.21 degree RMS error across 840MHz?960MHz,maintaining a good control accuracy of phase and amplitude.Applying this power amplifier to the self-jammer caceller,considering a 8 dBm self-jammer signal,results show that the maximum cancellation ratio can be 38dB.A full-integrated linear power amplifier is designed for UHF RFID transmitter.An active balun with error-correction function is used as driver stage,meanwhile,it performs single-to-differential conversion at the PA input,which can save some chip area.In order to achieve full integration,an on-chip transformer is adopted in the output matching network and it performs differential-to-single conversion at the PA output.The power amplifier is implemented in a 130nm CMOS process,and the core area is only 0.83 mm2.Post Simulation results show that the PA achieves a maximum output of 27 dBm with 41%PAE.Higher peak to average power ratio(PAPR)modulation schemes are used in modern wireless communication to achieve better spectral efficiency and support higher data rate,which means the PA must operate at power back-off level.To improve the back-off efficiency,this thesis presents a dual-mode power amplifier with a dynamic mode-switching scheme.By analyzing the power loss of CMOS switched capacitor structure under off-state,a high withstand voltage CMOS switched capacitor is adopted in tunable matching network to reduce power leakage at high output power level.By means of dynamically tuning the PA bias,transistor size and optimal load with a power detect controller,the PA's PAE is improved 11.7%at 7dB back off level.For 40MHz 802.1 In OFDM 64-QAM modulated signals,ACPR and EVM requirement of standard are well-confined at 18dBm output power.