Design Of High-Efficiency CMOS Power Amplifier For Wireless Sensor Networks Application

In recent years,with the development of sensor equipment and wireless communication technology,wireless sensor network has received great attention.The wide use of wireless sensor network makes it easier to monitor the physical environment remotely,but its characteristics such as low power consumption,small cost and limited network life bring a series of challenges to the transceiver system,especially to the design of power amplifier.Based on this background,the research of high-efficiency CMOS power amplifier is carried out in this thesis.In this paper,the application of power amplifier in wireless sensor network is analyzed.The architecture,technology and performance of CMOS power amplifier proposed at home and abroad are investigated.The basic theory of circuit design,such as power amplifier classification and performance parameters,is introduced.Then the key points to be considered are analyzed,including the nonlinear characteristics of the transistor and the impedance matching technology of the circuit.Then the corresponding high efficiency and linearization upgrading technology is proposed.On this basis,this paper presents a CMOS power amplifier with high efficiency.The power amplifier adopts single-terminal two-stage cascade structure,the drive stage and power stage both adopt self-offset cascode structure,which reduces the breakdown risk,increases the output voltage swing amplitude and improves the reverse isolation degree.The power stage offset is deep AB class,which improves the efficiency of the circuit and ensures a certain degree of linearity.The nonlinear effect caused by parasitic capacitance of transistor gate source is solved by capacitor compensation technology,and the gain and linearity of circuit are compromised by RC negative feedback technology.Input circuit using loadpull technology to select the optimum load impedance values,and using low pass 50?L-type matching network will transform as the best load impedance value,to nonlinear signal circuit of high order harmonic suppression,finally,the circuit achieves high output power and power added efficiency at the same time.This design is based on SMIC 55 nm RF CMOS process,using Cadencevirtuoso software to complete the whole 2.4GHz power amplifier circuit simulation,and using process Angle simulation to analyze the influence of component deviation on the circuit performance.In order to reduce the influence of parasitic effect of on-chip inductors,the design also carried out electromagnetic simulation optimization on the key modules of the circuit,and set up Cadence and Sonnet electromagnetic co-simulation platform to carry out electromagnetic co-simulation verification of the circuit.The chip area of the final circuit is 0.635mm~2,S11<-11.6 d B,the compression point of input 1d B is 1.5 d Bm,the saturated output power is 13.1 d Bm,and the power additional efficiency is 46%,all of these can meet the performance index.