The Influence On VLSI Design Performance By Constraints In Floorplanning

With the rapid development of modern chip technology,the design method of SoC(System-on-Chip)has become a mainstream.The design becomes more complicated due to increasing integrated modules on one single chip.Through the design method of SoC,reduced cost of the chip design and optimization of the chip area,greatly improving the overall performance of the chip.Physical design plays a key role in VLSI,and widely used method of hierarchical classification,generally divided into partitioning,floorplanning,place and route,etc.The floorplanning plays a vital role to the final VLSI performance because it is in the earlier stage of the physical design,especially in SoC.In this paper,we introduce some algorithms in the VLSI physical design,including the partition algorithm,representation floorplanning,place algorithm and routing algorithm,and we also make simple introduction of floorplanning constraints,including alignment constraint,abutment constraints,pre-place constraints,boundary constraints and clustering constraints.We proposed the floorplanning constraints embedding algorithm,and studied the influence of floorplanning constraints on VLSI hierarchical design performance by embedded floorplanning constraints into IBM-HB+ Benchmark.Pre-assignment constraints experiment shows that the chip design area,HPWL and whitespace proportion has a certain degree of reduction and running time basic remain unchanged.Analysis the results of placing,we found that the circuit HPWL and running time are increased.The results of routing shows that embedded floorplanning constraints increased the length running time.Post-assignment constraint experiment shows that the module proportion of embedded constraints,different constraints and module proportion make different influence in physical design,and HPWL is increased as the proportion increased.