Research On The Floorplanning Algorithm With Constrainst Of The VLSI

With the development of SOC designs, in modern hierarchical designs, many researchers add some extra constraints into the floorplanning optimization process to meet the different performance and reliability requirements, such as fixed-outline constraint, boundary constraint, alignment constraint, abutment constraint and so on. Some power integrity constraints are also considered in the floorplan design process, such as IR-drop constraints, minimum width constraints and electro migration constraints.A critical problem of floorplanning is the representation of geometric relationship among modules. In this thesis, the B*-Tree representation is applied for its simple, yet effective binary tree structure.This thesis focuses on the boundary clustering constraint which our proposed. It handles with the Marco modules which required constrained modules being on the boundaries or clustering to the boundaries. The boundary clustering constraint can help to minimize the wire length and routing space fragmentation. In order to effectively search the feasible solutions, the feasible conditions based on B*-tree representation with boundary clustering constraint are investigated. The properties, coupled with an efficient simulated annealing algorithm, provide the way to produce feasible floorplan by dynamic repairing, which can transform an infeasible solution into a feasible one if the constraint is violated. The proposed algorithm is verified by using the MCNC and GSRC benchmarks. The experimental results show that our algorithm which solves the floorplanning with boundary clustering constraint can obtain promising solutions in acceptable time.As the design complexity increases dramatically, it is necessary to handle the power constraints earlier in the design cycle for better design convergence. In this thesis, we do some deeply research on the power/ground network and floorplan co-design. The objective of co-design is to obtain a feasible floorplan and simultaneously generate a corresponding P/G network with minimal wiring resource while the power constraints are satisfied. In this thesis, we set up a pattern selection scheme for fast signal-integrity estimation. Using pattern selection method can significantly speed up the optimization process. We also propose a guided incremental floorplanning approach to amend the violations intelligently during the floorplanning process. At the same time, to minimize the area of P/G network, the P/G pin assignment and wire sizing method are also embedded in the floorplanning optimization process. Experimental results show that our design not only significantly speeds up the optimization process, but also optimize the power routing resource with maintaining the quality of the floorplan.